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m m b b 8 8 6 6 2 2 9 9 3 3 < < c c o o r r a a l l _ _ l l q q > > g g r r a a p p h h i i c c s s c c o o n n t t r r o o l l l l e e r r s s p p e e c c i i f f i i c c a a t t i i o o n n s s revision 1.1 14th jan, 2003 copyright ? fujitsu limited 2001 all rights reserved
ii the specifications in this manual are subject to change without notice . co ntact our sales department before purchasing the product described in this manual. information and circuit diagrams in this manual are only examples of device application s , they are not intended to be used in actual equipment. also, fujitsu accepts no res ponsibility for infringement of patents or other rights owned by third parties caused by use of the information and circuit diagrams. the contents of this manual must not be reprinted or duplicated without permission of fujitsu. fujitsu ? s semiconductor dev ices are intended for standard uses (such as office equipment (computers and oa equipment), industrial/communications/measuring equipment, and personal /home equipment). customers using semiconductor devices for special applications ( including aerospace , n uclear, military and medical applications) in which a failure or malfunction might endanger life or limb and which require extremely high reliability must contact our sales department first. if damage is caused by such use of our semiconductor devices wit hout first consulting our sales department, fujitsu will not assume any responsibility for the loss. semiconductor devices fail with a known probability. customers must use safety design (such as redundant design, fireproof design, over - current prevention design, and malfunction prevention design) so that failures will not cause accidents, injury or death). if the products described in this manual fall within the goods or technologies regulated by the f oreign e xchange and foreign trade law, permission must be obtained before exp orting the goods o r technologies.
update history date version page count change 2001.2.22 0.1 31 first edition 2001.7.23 0.2 228 see separate paper (page count difference between orchid and coral) 2001.8.23 0.3 238 see separate paper (page count difference between rev0.2 and rev0.3) 2001.11.12 0.4 262 see separate paper (page count difference between rev0.3 and rev0.4) 2001.12.8 0.5 266 see separate paper (page count difference between rev0.4 and rev0.5) 2002.1.9 0.6 266 see separate paper (page count difference between rev0.5 and rev0.6) 2002.4.15 0.7 274 see separate paper (page count difference between rev0.6 and rev0.7) 2002.5.21 0.8 274 see separate paper (page count difference between rev0.7 and re v0.8) 2003.1.14 1.1 284 see separate paper (page count difference between rev0.8 and rev1.1)
contents 1 general ................................ ................................ ................................ ............................ 10 1.1 p reface ................................ ................................ ................................ ......................... 10 1.2 f eatures ................................ ................................ ................................ ....................... 11 1.3 b lock d iagram ................................ ................................ ................................ .............. 12 1.4 f unctio nal o verview ................................ ................................ ................................ ..... 13 1.4.1 host cpu interface ................................ ................................ ................................ . 13 1.4.2 external memory interface ................................ ................................ ..................... 15 1.4.3 display controller ................................ ................................ ................................ ... 16 1.4.4 geometry processing ................................ ................................ ............................... 18 1.4.5 2d drawing ................................ ................................ ................................ ............ 19 1.4.6 3d drawing ................................ ................................ ................................ ............ 21 1.4.7 special effects ................................ ................................ ................................ ......... 2 2 1.4.8 others ................................ ................................ ................................ .................... 25 2 pins ................................ ................................ ................................ ................................ .... 26 2.1 s ignals ................................ ................................ ................................ .......................... 26 2.1.1 signal lines ................................ ................................ ................................ ............. 26 2.2 p in a ssignme nt ................................ ................................ ................................ .............. 27 2.2.1 pin assignment diagram ................................ ................................ ......................... 27 2.2.2 pin assignment table ................................ ................................ .............................. 28 2. 3 p in f unction ................................ ................................ ................................ .................. 30 2.3.1 host cpu interface ................................ ................................ ................................ . 30 2.3.2 video output interface ................................ ................................ ............................. 32 2.3.3 graphics memory interface ................................ ................................ ..................... 33 2.3.4 clock input ................................ ................................ ................................ ............. 34 2.3.5 test pins ................................ ................................ ................................ ................. 35 2.3.6 reset sequence ................................ ................................ ................................ ....... 35 3 procedure of the har dware initialization ................................ ........................... 36 3.1 h ardware reset ................................ ................................ ................................ ............ 36 3.2 r e - reset ................................ ................................ ................................ ....................... 36 3.3 s oftware reset ................................ ................................ ................................ ............. 36 4 host interface ................................ ................................ ................................ ............... 37 4.1 o peration m ode ................................ ................................ ................................ ............ 37 4.1.1 host cpu mode ................................ ................................ ................................ ...... 37 4.1.2 ready signal mode ................................ ................................ ................................ .. 37 4.1.3 bs signal mode ................................ ................................ ................................ ....... 38
4.1.4 endian ................................ ................................ ................................ .................... 38 4.2 a ccess m ode ................................ ................................ ................................ ................. 39 4.2.1 sram interface ................................ ................................ ................................ ...... 39 4.2.2 fifo interface (fixed transfer destination address) ................................ ................. 39 4.3 dma t ransfer ................................ ................................ ................................ ............... 40 4.3.1 data transfer unit ................................ ................................ ................................ ... 40 4.3.2 address mode ................................ ................................ ................................ ......... 40 4.3.3 bus mode ................................ ................................ ................................ ................ 41 4.3.4 dma transfer request ................................ ................................ ............................. 41 4.3.5 ending dma transfer ................................ ................................ ............................. 41 4.4 t ransfer of l ocal d isp lay l ist ................................ ................................ ..................... 42 4.5 i nterrupt ................................ ................................ ................................ ...................... 43 4.6 sh3 m ode ................................ ................................ ................................ ...................... 43 4.7 w ait ................................ ................................ ................................ .............................. 43 4.8 m emory m ap ................................ ................................ ................................ .................. 44 5 graphics memory ................................ ................................ ................................ ........... 46 5.1 c onfiguration ................................ ................................ ................................ ............... 46 5.1.1 data type ................................ ................................ ................................ ................ 46 5.1.2 memory mapping ................................ ................................ ................................ .... 47 5.1.3 data format ................................ ................................ ................................ ........... 47 5.2 f rame m anagement ................................ ................................ ................................ ....... 49 5.2.1 single buffer ................................ ................................ ................................ .......... 49 5.2.2 double buffer ................................ ................................ ................................ ......... 49 5.3 m emory a ccess ................................ ................................ ................................ ............. 49 5.3.1 memory access by host cpu ................................ ................................ ................... 49 5.3.2 priority of memory accessing ................................ ................................ .................. 49 5.4 c onnection with memor y ................................ ................................ ............................... 50 5.4.1 connection with memory ................................ ................................ ........................ 50 6 display con troller ................................ ................................ ................................ ...... 52 6.1 o verview ................................ ................................ ................................ ....................... 52 6.2 d isplay f unction ................................ ................................ ................................ ........... 52 6.2.1 layer configu ration ................................ ................................ ................................ 52 6.2.2 overlay ................................ ................................ ................................ ................... 54 6.2.3 display parameters ................................ ................................ ................................ 56 6.2.4 display p osition control ................................ ................................ .......................... 57 6.3 d isplay c olor ................................ ................................ ................................ ............... 59 6.4 c ursor ................................ ................................ ................................ .......................... 60 6.4.1 cursor dis play function ................................ ................................ ........................... 60 6.4.2 cursor control ................................ ................................ ................................ ......... 60
6.5 d isplay s can c ontrol ................................ ................................ ................................ ... 61 6 .5.1 applicable display ................................ ................................ ................................ ... 61 6.5.2 interlace display ................................ ................................ ................................ ..... 62 6.6 t he external synchron ous signal ................................ ................................ ................. 63 6.7 v ideo i nterface , ntsc/pal o utput ................................ ................................ ............... 66 7 geometry engine ................................ ................................ ................................ ........... 67 7.1 g eometry p ipeline ................................ ................................ ................................ ......... 67 7.1.1 processing flow ................................ ................................ ................................ ....... 67 7.1.2 model - view - projection (mvp) transformation (oc ? cc coordinate transformation) 68 7.1.3 3d - 2d transformation (cc ? ndc coordinate transformation) ................................ 68 7.1.4 view port transformation (ndc ? dc coordinate transformation) ........................... 69 7.1.5 view volume clipping ................................ ................................ .............................. 69 7.1.6 back face curling ................................ ................................ ................................ .... 71 7.2 d ata f ormat ................................ ................................ ................................ .................. 72 7.2.1 data format ................................ ................................ ................................ ............ 72 7.3 s etup e ngine ................................ ................................ ................................ ................. 73 7.3.1 setup processing ................................ ................................ ................................ ..... 73 7.4 l og o utput of d evice c oordinates ................................ ................................ ............... 73 7.4.1 log output mode ................................ ................................ ................................ ..... 73 7.4.2 log output destination address ................................ ................................ ............... 73 8 drawing processing ................................ ................................ ................................ ..... 74 8.1 c oordinate s ystem ................................ ................................ ................................ ....... 74 8.1.1 drawing coordinates ................................ ................................ ............................... 74 8.1.2 texture coordinates ................................ ................................ ................................ 75 8.1.3 frame buffer ................................ ................................ ................................ .......... 76 8.2 f igure d raw ing ................................ ................................ ................................ ............. 77 8.2.1 drawing primitives ................................ ................................ ................................ . 77 8.2.2 polygon drawing function ................................ ................................ ....................... 77 8 .2.3 drawing parameters ................................ ................................ ............................... 78 8.2.4 anti - aliasing function ................................ ................................ ............................. 79 8.3 b it m ap p rocessing ................................ ................................ ................................ ....... 80 8.3.1 blt ................................ ................................ ................................ ........................ 80 8.3.2 pattern data format ................................ ................................ ................................ 80 8.4 t exture m apping ................................ ................................ ................................ ........... 81 8.4.1 texture size ................................ ................................ ................................ ............ 81 8.4.2 texture color ................................ ................................ ................................ ........... 81 8.4.3 texture lapping ................................ ................................ ................................ ...... 82 8.4.4 filtering ................................ ................................ ................................ ................. 83 8.4.5 perspective correction ................................ ................................ ............................. 83
8.4.6 texture blending ................................ ................................ ................................ ..... 84 8.4.7 bi - linear high - speed mode ................................ ................................ ...................... 84 8.5 r endering ................................ ................................ ................................ ..................... 86 8.5.1 tiling ................................ ................................ ................................ ...................... 86 8.5.2 alpha blending ................................ ................................ ................................ ....... 86 8.5.3 logic operation ................................ ................................ ................................ ....... 87 8.5.4 hidden plane management ................................ ................................ ..................... 87 8.6 d rawing a ttributes ................................ ................................ ................................ ....... 88 8.6.1 line drawing attributes ................................ ................................ .......................... 88 8.6.2 triangle drawing attributes ................................ ................................ .................... 88 8.6.3 texture attributes ................................ ................................ ................................ ... 89 8.6.4 blt attributes ................................ ................................ ................................ ........ 90 8.6.5 character pattern dra wing attributes ................................ ................................ ..... 90 8.7 b old l ine ................................ ................................ ................................ ....................... 91 8.7.1 starting and ending points ................................ ................................ ..................... 91 8.7.2 broken line pattern ................................ ................................ ................................ 92 8.7.3 edging ................................ ................................ ................................ .................... 93 8.7.4 interpolation of bold line joint ................................ ................................ ................. 94 9 display list ................................ ................................ ................................ ...................... 95 9.1 o verview ................................ ................................ ................................ ....................... 95 9.1.1 header format ................................ ................................ ................................ ........ 96 9.1.2 parameter format ................................ ................................ ................................ ... 96 9.2 g eometry c ommands ................................ ................................ ................................ ..... 97 9.2.1 geometry command list ................................ ................................ .......................... 97 9.2.2 explanation of geometry commands ................................ ................................ ...... 100 9.3 r endering c ommand ................................ ................................ ................................ .... 110 9.3.1 command list ................................ ................................ ................................ ....... 110 9.3.2 details of rendering commands ................................ ................................ ............. 115 10 register ................................ ................................ ................................ ......................... 125 10.1 r egister l ist ................................ ................................ ................................ ............... 125 10.1.1 host interface register list ................................ ................................ .................... 125 10.1.2 graphics memory interface register list ................................ ................................ 127 10.1.3 display controller register list ................................ ................................ .............. 128 10.1.4 drawing engine register list ................................ ................................ .................. 133 10.1.5 geometry engine register list ................................ ................................ ................ 139 10.2 e xplanation of r egister ................................ ................................ ............................. 140 10.2.1 host interface registers ................................ ................................ ......................... 141 10.2.2 graphics memory interface registers ................................ ................................ .... 148 10.2.3 display control register ................................ ................................ ......................... 151
10.2.4 drawing control registers ................................ ................................ ..................... 199 10.2.5 drawing mode registers ................................ ................................ ........................ 202 10.2.6 triangle drawing registers ................................ ................................ .................... 220 10.2.7 lin e drawing registers ................................ ................................ .......................... 223 10.2.8 pixel drawing registers ................................ ................................ ......................... 224 10.2.9 rectangle drawing registers ................................ ................................ .................. 224 10.2.10 blt registers ................................ ................................ ................................ ...... 225 10.2.11 high - speed 2d line drawing registers ................................ ................................ 226 10.2.12 high - speed 2d triangl e drawing registers ................................ .......................... 227 10.2.13 geometry control register ................................ ................................ .................. 228 10.2.14 geometry mode registers ................................ ................................ ................... 230 10.2.15 display list fifo registers ................................ ................................ ................ 237 11 timing diagram ................................ ................................ ................................ .............. 238 11.1 h ost i nterface ................................ ................................ ................................ .... 238 11.1.1 cpu read/write timing diagram in sh3 mode (normally not ready mode) ........... 238 11.1.2 cpu read/write timing diagram in sh3 mode (normally ready mode) ................. 239 11.1.3 cpu read/write timing diagram in sh4 mode (normally not ready mode) ........... 240 11.1.4 cpu read/write timing diagram in sh4 mode (normally ready mode) ................. 241 11.1.5 cpu read/write timing diagram in v832 mode (normally not ready mode) ......... 242 11.1.6 cpu read/write timi ng diagram in v832 mode (normally ready mode) ................ 243 11.1.7 cpu read/write timing diagram in sparclite (normally not ready mode) .......... 244 11 .1.8 cpu read/write timing diagram in sparclite (normally ready mode) ................. 245 11.1.9 sh4 single - address dma write (transfer of 1 long word) ................................ ....... 246 11.1.10 sh4 single - address dma write (transfer of 8 long words) ................................ .. 247 11.1.11 sh3/4 dual - address dma (transfer of 1 long word) ................................ ............ 248 11.1.12 sh3/4 dual - address dma (transfer of 8 long words) ................................ ........... 248 11.1.13 v832 dma transfer ................................ ................................ ........................... 249 11.1.14 sh4 single - address dma tran sfer end timing ................................ .................... 250 11.1.15 sh3/4 dual - address dma transfer end timing ................................ ................... 250 11.1.16 v832 dma transfer end timing ................................ ................................ .......... 251 11.1.17 sh4 dual dma write without ack ................................ ................................ .... 252 11.1.18 dual - address dma (without ack) end timing ................................ ................... 253 11.2 g raphics m emory i nterface ................................ ................................ ........................ 254 11.2.1 timing of read access to same row address ................................ ........................... 254 11.2.2 timing of read access to d ifferent row addresses ................................ ................... 255 11.2.3 timing of write access to same row address ................................ .......................... 256 11.2.4 timing of write access to different row addr esses ................................ .................. 257 11.2.5 timing of read/write access to same row address ................................ .................. 258 11.2.6 delay between actv commands ................................ ................................ ........... 259
11.2.7 delay between refresh command and next actv command ................................ . 259 11.3 d isplay t iming ................................ ................................ ................................ .............. 260 11.3.1 non - interlace mode ................................ ................................ ............................... 260 11.3.2 interlace video mode ................................ ................................ ............................. 261 11.3.3 composite synchronous signal ................................ ................................ .............. 262 11.4 cpu c autions ................................ ................................ ................................ ............. 262 11.5 sh3 m ode ................................ ................................ ................................ .................... 263 11.6 sh4 m ode ................................ ................................ ................................ .................... 263 11.7 v832 m ode ................................ ................................ ................................ .................. 264 11.8 sparc lite ................................ ................................ ................................ ................... 264 11.9 s upported dma t ransfer m odes ................................ ................................ ................ 264 12 electrical character istics ................................ ................................ .................... 265 12.1 i ntroduction ................................ ................................ ................................ ............... 265 12.2 m aximum r ating ................................ ................................ ................................ ........... 265 12.3 r ecommended o perating c onditions ................................ ................................ ........... 266 12.3.1 recommended operating conditions ................................ ................................ ...... 266 12.3.2 note at po wer - on ................................ ................................ ................................ .. 266 12.4 dc c haracteristics ................................ ................................ ................................ .... 268 12.4.1 dc characteristics ................................ ................................ ............................... 268 1 2.4.2 v - i characteristics diagram ................................ ................................ ................... 269 12.5 ac c haracteristics ................................ ................................ ................................ .... 270 12.5.1 host interface ................................ ................................ ................................ ....... 270 12.5.2 video interface ................................ ................................ ................................ ...... 271 12.5.3 graphics memory interface ................................ ................................ ................... 272 12.5.4 pll specifications ................................ ................................ ................................ . 276 12.6 ac c haracteristics m easuring c onditions ................................ ................................ . 277 12.7 t iming d iagram ................................ ................................ ................................ ............ 278 12.7.1 host i nterface ................................ ................................ ................................ ....... 278 12.7.2 video interface ................................ ................................ ................................ ...... 282 12.7.3 graphics memory interface ................................ ................................ ................... 283
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 1 0 specifications rev. 1.1 1 general 1.1 preface coral graphics controller has some functions and optional efficiency and is planned to be serial - manufactured according to purposes . for es version, the specifications in which common descriptions to coral series are written are planned to provide and for mass - production version, the specifications which are unique to each series are planed to be provided. therefore, please bear in mind that the contents for es and mass - production versions may be different form each other.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 11 specifications rev. 1.1 1.2 features geometry engine geometry en gine supports the geometry processing that is compatible with orchid (mb86292). using the display list created by orchid enables drawing. **(but floating point setup command is deleted.) heavy processing of geometric operations such as coordinates convers ions or clipping performed by this device can reduce the cpu loads dramatically. 2d and 3d drawing coral has a drawing function that is compatible with the cremson ( mb86290a ) . it can draw data using the display list created for cremson . **(but internal t exture ram is deleted.) coral also supports 3d rendering, such as texture mapping with perspective collection and gouraud shading, alpha b l ending, and anti - aliasing for drawing smooth lines. display controller coral has a display controller that is compati ble with orchid . in addition to the traditional xga (1024 768 pixels) display, 4 - layer overlay, left/right split display, wrap - around scrolling, double buffers, and translucent display, function of 6 - layer overlay, 4 - siding for palette are expanded. host cpu interface can be connected to sh3 and sh4 manufactured by hitachi, to v832 microprocessor by nec and to sparclite (mb86833) by fujitsu without external circuits. external memory interface sdram and fcram can be connected. optional function final devic e can be selected either geometry high - /low - speed version. others cmos technology with 0. 18 - m hqfp256 package (lead pitch 0. 4 mm) supply voltage: 1. 8 v (internal operation) /3.3 v (i/o) current consumption ( typical ) 1.8 v power supply : 500ma 3.3v power supply : 100ma
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 12 specifications rev. 1.1 1.3 block diagram coral general block diagram is shown below: please note that the capture controller is deleted from this figure in coral - lq. fig.1. 1 coral block diagram d0 - 31 host interface external memory controller display controller geometry engine 2d/3d rendering engine d rgb a2 - 25 pixel bus md0 - 31/63 ma0 - 14 sdram or fcram external bus of host cpu
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 13 specifications rev. 1.1 1.4 functional overview 1.4.1 host cpu interface s upported cpu coral can be connected to sh3 and sh4 manufactured by hitachi , v832 by nec , sparclite (mb86833) by fujitsu . external bus clock can be connected at max. 100 mhz (when using sh4 interface) ready mode supports normal ready/not ready. endian suppo rts little e ndian . access mode sram interface fifo interface (transfer destination address fixed) dma transfer supports 1 - double word (32 bits) /8 - double word (32 bytes) (only sh4) for transfer unit. ack used/unused mode can be selected as protocol (only f or dam in dual address mode) supports dual address/mode single address mode (only sh4). supports cycle steel/burst. supports local display list transfer. interrupt vertical (frame) synchronous detection field synchronous detection external synchronous erro r detection drawing command error drawing command execution end
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 14 specifications rev. 1.1 switching internal operating frequency switch the operating frequency immediately after a reset (before rewriting mmr mode register of external memory interface). any operating frequency can be selected from the five combinations shown in table 2 - 6 . table 1 - 1 frequency setting combinations clock for geometry engine clock for other than geometry engine 166 mhz 133 mhz 166 mhz 100 mhz 133 mhz 133 mhz 133 mhz 100 mhz 100 mhz 100 mhz the fo llowing relationship is disabled: clock for geometry engine < clock for other than geometry engine
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 15 specifications rev. 1.1 1.4.2 external memory interface sdram or fcram can be connected. 64 bits or 32 bits can be selected for data bus. max. 133 mhz is available for operating freque ncy. connectable memory configuration is as shown below. external memory configuration type data bus width use count total capacity fcram 16 m b it s (x 16 bit s ) 32 bit s 2 4 m bytes fcram 16 mbit s (x16 bit s ) 64 bit s 4 8 m bytes sdram 64 mbit s (x32 bit s ) 32 bi t s 1 8 m bytes sdram 64 mbit s (x32 bit s ) 64 bit s 2 16 m bytes sdram 64 mbit s (x16 bit s ) 32 bit s 2 16 m bytes sdram 64 mbit s (x16 bit s ) 64 bit s 4 32 m bytes sdram 128 mbit s (x32 bit s ) 32 bit s 1 16 m bytes sdram 128 mbit s (x32 bit s ) 64 bit s 2 32 m bytes sdra m 128 mbit s (x16 bit s ) 32 bit s 2 32 m bytes sdram 128 mbit s (x16 bit s ) 64 bit s 4 64 m bytes sdram 256 mbit s (x16 bit s ) 32 bit s 2 64 m bytes
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 16 specifications rev. 1.1 1.4.3 display c ontroller video data output each 6 - bit digital video output is provided. screen resolution lcd panels wi th wide range of resolutions are supported by using a programmable timing generator as follows: screen resolutions resolution s 1024 768 1024 600 800 600 854 480 640 480 480 234 400 234 320 234 hardware cursor coral supports two ha rdware cursor functions. each of these hardware cursors is specified as a 64 64 - pixel area. each pixel of these hardware cursors is 8 bits and uses the same look - up table as indirect color mode . double buffer method double buffer method in which drawin g window and display window is switched in units of 1 frame enables the smooth animation. flipping (switching of display window area) is performed in synchronization with the vertical blanking period using program. scroll method independent setting of draw ing and display windows and their starting position enables the smooth scrolling. display colors supports indirect color mode which uses the look - up table (color pale t t e ) in 8 bits/pixels. entry for look - up table (color palette) corresponds to color code for 8 bits, in other words, 256 . color data is each 6 bits of rgb. consequently, 256 colors can be displayed out of 260,000 colors. supports direct color mode which specifies rgb with 16 bits/pixels.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 17 specifications rev. 1.1 overlay compatibility mode up to four extra layers (c , w, m and b) can be displayed overlaid. the overla y position for the hardware cursors is above/below the top layer (c). the transparent mode or the blend mode can be selected for overlay. the m - and b - layers can be split into separate windows. window disp lay can be performed for the w - layer. two palettes are provided: c - layer and m - /b - layer. the w - layer is used as the video input layer. window mode up to six screens (l0 to 5) can be displayed overlaid. the overlay sequence of the l0 - to l5 - layers can be changed arbitrarily. the overla y position for the hardware cursors is above/below the l0 - layer. the transparent mode or the blend mode can be selected for overlay. the l5 - layer can be used as the blend coefficient plane (8 bits/pixel). window display can be performed for all layers. four palettes corresponded to l0 to 3 are provided. the l1 - layer is used as the video input layer. background color display is supported in window display for all layers. l0, l2, l4 ( 0,0 ) l3, l5 ( hdb + 1 , 0) l1 ( wx, wy ) l0 ( l0wx, l0wy ) l2 ( l2wx, l2wy ) l1 ( l1wx, l1wy ) l5 ( l5wx, l5wy ) l4 ( l4wx, l4wy ) l3 ( l3wx, l3wy )
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 18 specifications rev. 1.1 1.4.4 geometry p rocessi ng coral has a geometry engine for performing the numerical operations required for graphics processing. the geometry engine uses the floating - point format for highly precise operations. it selects the required geometry processing according to the set dr awing mode and primitive type and executes processing to the final drawing. primitives point , line , line strip , independent triangle , triangle strip , triangle fan , and arbitrary polygon are supported. mvp transformation mvp transformation setting a 4 4 t ransformation matrix enables transformation of a 3d model view projection. two - dimensional af f ine transformation is also possible. clipping clipping stops drawing of figures outside the window (field of view). polygons (including concave shapes) can also be clipped. culling triangles on the back are not drawn. 3d - 2d transformation this functions transforms 3d coordinates (normalization) into 2d coordinates in orthogonal or perspective projections. view port transformation this function transforms normaliz ed 2d coordinates into drawing (device) coordinates. primitive setup this function automatically performs a variety of slope computations, etc., based on transforming vertex data into coordinates and prepares for rendering (setup) . log output of device coo rdinates the view port conversion results are output to the local memory.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 19 specifications rev. 1.1 1.4.5 2d d rawing 2d primitives coral can perform 2d drawing for graphics memory (drawing plane) in direct color mode or indirect color mode. bold lines with width and broken lines can be drawn. with anti - aliasing smooth diagonal lines also can be drawn. a triangle can be tiled in a single color or 2d pattern (tiling), or mapped with a texture pattern by specifying coordinates of the 2d pattern at each vertex (texture mapping). at textur e mapping, drawing/non - drawing can be set in pixel units. moreover, transparent processing can be performed using alpha blending. when drawing in single color or tiling without gouraud shading or texture mapping, high - speed 2d line and high - speed 2dtriang le can be used. only vertex coordinates are set for these primitives. high - speed 2d t riangle is also used to draw polygons. 2d primitives primitive type description point plots point line draws line bold line strip (provisional name) draws continuous bold line this primitive is used when interpolating the bold line joint. triangle draws triangle high - speed 2dline draws lines compared to line, this reduce s the host cpu processing load. arbitrary polygon draws arbitrary closed polygon containing conca ve shapes consisting of vertices arbitrary polygon draw ing using this function , arbitrary closed polygon containing concave shapes consisting of vertices can be drawn . ( there is no restriction on the count of vertices, however, the polygon with its side s crossed are not supported. ) in this case, as a work area for drawing, polygon draw ing flag buffer is used on the graphics memory . in drawing polygon, draw triangle for polygon drawing flag buffer using high - speed 2dtriangle. decide any vertex as a sta rting point to draw triangle along the periphery. it enables you to draw final polygon form in singl e color or with tiling/texture mapping in a draw ing frame.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 20 specifications rev. 1.1 blt/rectangle drawing this function draws a rectangle using logic operations . it is used to dr aw pattern and copy the image pattern within the drawing frame . it is also used for clearing drawing frame and z buffer . blt attributes attribute description raster operation selects two source logical operation mode transparent processing performs blt without drawing pixel consistent with the transparent color. alpha blending the alpha map and source in the memory is subjected to alpha blending and then copied to the destination. pattern (text) drawing this function draws a binary pattern (text) in a specified color. pattern (text) drawing attributes attribute description enlarge vertically 2 2 horizontally 2 vertically and horizontally 2 shrink vertically 1/2 1/2 horizontally 1/2 vertically and horizontally 1/2 drawing clipping this fun ction sets a rectang le frame in drawing frame to prohibit the drawing of the outside the frame .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 21 specifications rev. 1.1 1.4.6 3d d rawing 3d primitives this function draws 3d objects in drawing memory in the direct color mode. 3d primitives primitive description point plots 3d point line draws 3d line triangle draws 3d triangle arbitrary polygon draws arbitrary closed polygon containing concave shapes consisting of vertexes 3d drawing attributes texture mapping with bi - linear filtering/automatic perspective correction and gouraud shading provides high - quality realistic 3d drawing. a built - in texture mapping unit performs fast pixel calculations. this unit also delivers color blending between the shading color and texture color. hidden plane management coral supports the z buffer for hidden plane management.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 22 specifications rev. 1.1 1.4.7 special e ffects anti - aliasing anti - aliasing manipulates line borders of polygons in sub - pixel units and blend the pre - drawing pixel color with color to make the jaggies be seen smooth . it is used as a functional option for 2 d drawing (in direct color mode only). bold line and broken line drawing this function draws lines of a specific width and a broken line . line draw ing attributes attribute description line width selectable from 1 to 32 pixels broken line set by 32 bit o r 24 bit of broken line pattern supports the verticality of starting and ending points. supports the verticality of broken line pattern. interpolation of bold line joint supports the following modes: ( 1) broken line pattern reference address fix mode ? t he same broken line pattern is kept referencing for the period of some pixels starting from the joint and the starting point for the next line. ( 2) no interpolation supports the equalization of the width of bold lines. supports the bold line edging. not su pport the anti - aliasing of dashed line patterns. for a part overlaid due to connection of bold lines, natural overlay can be represented by providing depth information. (z value). shading supports the shading primitive. drawing is performed to the body pr imitive coordinates (x, y) with an offset as a shade. at this drawing, the z buffer is used in order to differentiate between the body and shade.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 23 specifications rev. 1.1 alpha blending alpha blending blends two image colors to provide a transparent effect. coral supports two types of blending; blending two different colors at drawing, and blending overlay planes at display. transparent color is not used for these blending options. there are two ways of specifying alpha blending for drawing: ( 1) set a transparent coefficient t o the register; the transparent coefficient is applied for transparency processing of one plane. ( 2) set a transparent coefficient for each vertex of the plane; as with gouraud shading, the transparent coefficient is linear - interpolated to perform transpar ent processing in pixel units. in addition to the above, the following setting s can be performed at texture mapping . w hen the most significant bit of each texture cell is 1, drawing or transparency can be set. w hen the most significant bit of each textur e cell is 0, non - drawing can be set. alpha blending type description drawing transparent ratio set in particular register while one primitive (polygon, pattern, etc.), being drawn, registered transparent ratio applied a transparent coefficient set for eac h vertex. a l inear - interpolated transparent coefficient applied. this is possible only in direct color mode. overlay display blends top layer pixel color with lower layer pixel color transparent coefficient set in particular register registered transpare nt coefficient applied during one frame scan gouraud shading gouraud shading can be used in the direct color mode to provide 3d object real shading and color gradation. gray scale gouraud shading gray scale g ouraud shading can be used in the in - direct c olor (8bit/pixel) mode to draw a blend coefficient layer .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 24 specifications rev. 1.1 texture mapping coral supports texture mapping to map a n image pattern onto the surface of plane . the texture pattern can be laid out in the graphics memory. in this case, max. 4096 4096 pixels can be used. for drawing 8 - bit color, only point sampling can be specified for texture interpolation; only de - curl can be specified for the blend mode. texture mapping function description filtering point sample bi - linear filter coordinate s correction l inear perspective blend de - curl modulate stencil alpha blend normal stencil stencil alpha wrap repeat cramp border
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 25 specifications rev. 1.1 1.4.8 other s drawing color 8 - bit indirect color and 16 - bit direct color are supported as a drawing input data. top - left rule non - applicable mode in addition to the top - left rule applicable mode in which the triangle borders are compatible with cremson, the top - left rule non - applicable mode can be used. (in case of non - top - left polygon drawing, an object has to be in a geometry clipp ing area.) caution: use perspective correct mode when use texture at the top - left rule non - applicable mode. top - left rule non - applicable primitives cannot use geometry clip function. non - top - left - part ? s pixel quality is less than body. (usi ng approximate calculation)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 26 specifications rev. 1.1 2 pins 2.1 signals 2.1.1 signal lines fig. 2 .1 coral signal lines xrdy rdy_mode coral graphics controller testh host cpu interface hqfp256 d0 - 31 a2 - 25 bclki xrst xcs xrd xwe0 - 3 xbs dreq drack dtack bs_mode xint clk s clock ckm dclko dckli hsync vsync gv r2 - 7 video output interface dispe xrgben g2 - 7 b2 - 7 csync trst clksel0 - 1 md0 - 63 mcas mwe mras mclki mdqm0 - 7 mclko ma0 - 14 graphics memory interface test
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 27 specifications rev. 1.1 2.2 pin assignment 2.2.1 pin a ssignment d iagram note: the mode2 signal used for orchid is changed as shown below. mode2 signal for orchid ? r dy_mode signal for coral dtack xwe0 vddl xwe1 xwe2 xwe3 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 vddl a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 clksel0 vddl clksel1 vss vss clk pllvdd pllvss s trst testh testh dclki vss vss testh vddl testh vsync hsync vss vss csync gv de dclko vddh dr7 dr6 dr5 dr4 vddl dr3 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 drack 1 192 dr2 bs_mode 2 191 dg7 rdy_mode 3 190 dg6 xint 4 189 dg5 dreq 5 188 dg4 xrdy 6 187 dg3 vddh 7 186 dg2 vddl 8 185 db7 bclki 9 184 vddl xcs 10 183 db6 xrd 11 182 db5 xbs 12 181 db4 ckm 13 180 db3 mode0 14 179 db2 mode1 15 178 vddh mode2 16 177 vss xrst 17 176 vss vss 18 175 md63/r1 vss 19 174 md62/r0 d0 20 173 md61/g1 d1 21 172 md60/g0 d2 22 171 md59/b1 d3 23 170 md58/b0 vddl 24 169 md57 d4 25 168 vddl d5 26 167 md56 vddh 27 166 md55 d6 28 165 md54 d7 29 164 md53 d8 30 163 md52 d9 31 162 md51 d10 32 161 md50 d11 33 160 md49 d12 34 159 md48 d13 35 158 testh d14 36 157 testh d15 37 156 md47 d16 38 155 md46 d17 39 154 md45 vddl 40 153 md44 d18 41 152 vddl vddh 42 151 md43 d19 43 150 md42 d20 44 149 md41 d21 45 148 md40 d22 46 147 vss d23 47 146 vss d24 48 145 md39 d25 49 144 md38 d26 50 143 md37 d27 51 142 md36 d28 52 141 md35 d29 53 140 md34 d30 54 139 md33 d31 55 138 md32 vddl 56 137 xrgben vddh 57 136 testh vss 58 135 vddl vss 59 134 vss md0 60 133 vss md1 61 132 mclki md2 62 131 vddh md3 63 130 vss md4 64 129 vss 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 md5 vddl md6 md7 md8 md9 md10 md11 md12 md13 md14 md15 vddh md16 md17 md18 vddl md19 md20 md21 md22 md23 md24 md25 md26 md27 md28 md29 md30 md31 vddl vss vss vddh dqm0 dqm1 dqm2 dqm3 ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 vddl ma8 ma9 ma10 ma11 ma12 ma13 ma14 vddh mras mcas mwe dqm4 dqm5 dqm6 dqm7 vddl mclko
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 28 specifications rev. 1.1 2.2.2 pin a ssignment t able no. name no. name no. name no. name 1 drack 65 md5 129 vss 193 dr3 2 bs_mode 66 vddl 130 vss 194 vddl 3 rdy_mode 67 md6 131 vddh 195 dr4 4 xint 68 md7 132 mclki 196 dr5 5 dreq 69 md8 133 vss 197 dr6 6 xrdy 70 md9 134 vss 198 dr7 7 vddh 71 md10 135 vddl 199 vddh 8 vddl 72 md11 136 testh 200 dclko 9 bclki 73 md12 137 xrgben 201 de 10 xcs 74 md13 138 md32 202 gv 11 xrd 75 md14 139 md33 203 csync 12 xbs 76 md15 140 md34 204 vss 13 ckm 77 vddh 141 md35 205 vss 14 mode0 78 md16 142 md36 206 hsync 15 mode1 79 md17 143 md37 207 vsync 16 mode2 80 md18 144 md38 208 testh 17 xrst 81 vddl 145 md39 209 vddl 18 vss 82 md19 146 vss 210 testh 19 vss 83 md20 147 vss 211 vss 20 d0 84 md21 148 md40 212 vss 21 d1 85 md22 149 md41 213 dclki 22 d2 86 md23 150 md42 214 testh 23 d3 87 md24 151 md43 215 testh 24 vddl 88 md25 152 vddl 216 trst 25 d4 89 md26 153 md44 217 s 26 d5 90 md27 154 md45 218 pllvss 27 vddh 91 md28 155 md46 219 pllvdd 28 d6 92 md29 156 md47 220 clk 29 d7 93 md30 157 testh 221 vss 30 d8 94 md31 158 testh 222 vss 31 d9 95 vddl 159 md48 223 clksel1 32 d10 96 vss 160 md49 224 vddl 33 d11 97 vss 161 md50 225 clksel0 34 d12 98 vddh 162 md51 226 a2 35 d13 99 dqm0 163 md52 227 a3 36 d14 100 dqm1 164 md53 228 a4 37 d15 101 dqm2 165 md54 229 a5 38 d16 102 dqm3 166 md55 230 a6 39 d17 103 ma0 167 md56 231 a7 40 vddl 104 ma1 168 vddl 232 a8 41 d18 105 ma2 169 md57 233 a9 42 vddh 106 ma3 170 md58/b0 234 a10 43 d19 107 ma4 171 md59/b1 235 a11 44 d20 108 ma5 172 md60/g0 236 a12 45 d21 109 ma6 173 md61/g1 237 a13 46 d22 110 ma7 174 md62/r0 238 a14 47 d23 111 vddl 175 md63/r1 239 vddl 48 d24 112 ma8 176 vss 240 a15 49 d25 113 ma9 177 vss 241 a16 50 d26 114 ma10 178 vddh 242 a17 51 d27 115 ma11 179 db2 243 a18 52 d28 116 ma12 180 db3 244 a19 53 d29 117 ma13 181 db4 245 a20 54 d30 118 ma14 182 db5 246 a21 55 d31 119 vddh 183 db6 247 a22 56 vddl 120 mras 184 vddl 248 a23 57 vddh 121 mcas 185 db7 249 a24 58 vss 122 mwe 186 dg2 250 a25 59 vss 123 dqm4 187 dg3 251 xwe3 60 md0 124 dqm5 188 dg4 252 xwe2 61 md1 125 dqm6 189 dg5 253 xwe1 62 md2 126 dqm7 190 dg6 254 vddl 63 md3 127 vddl 191 dg7 255 xwe0 64 md4 128 mclko 192 dr2 256 dtack
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 29 specifications rev. 1.1 notes v ss /pllv ss : ground v ddh : 3.3 - v power supply v ddl /pllv dd : 1. 8 - v power supply pllv dd : pll power supply open : do not connect anything. testh : input a 3.3 v - power supply . - it is recommende d that pllv dd should be isolated on the pcb. - insert a bypass capacitor with good high frequency characteristics between the power supply and ground. place the capacitor as near as possible to the pin.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 30 specifications rev. 1.1 2.3 pin function 2.3.1 host cpu i nterface table 2 - 1 host c pu interface pins pin name i/o description mode0 - 2 input host cpu mode select rdy _ mode input normally ready, not ready select bs _ mode input bs signal with/without select xrst input hardware reset d0 - 31 in/out host cpu bus data a2 - a25 input host cpu b us address (in the v832 mode, a[24] is connected to xmwr.) bclki input host cpu bus clock xbs input bus cycle start signal xcs input chip select signal xrd input read strobe signal xwe0 input write strobe for d0 to d7 signal xwe1 input write strobe f or d8 to d15 signal xwe2 input write strobe for d16 to d23 signal xwe3 input write strobe for d24 to d31 signal xrdy output tri - state wait request signal (in the sh3 mode, when this signal is ?0?, it indicates the wait state; in the sh4, v832 and sparcl ite modes, when this signal is ?1?, it indicates the wait state.) dreq output dma request signal (this signal is low - active in both the sh mode and v832 mode.) drack/dmaak input acknowledge signal in response to dma request (dmaak is used in the v832 mod e; this signal is high - active in both the sh mode and v832 mode.) dtack/xtc input dma transfer strobe signal (xtc is used in the v832 mode. in the sh mode, this signal is high - active; in the v832 mode, it is low - active.) xint output interrupt signal iss ued to host cpu (in the sh mode, and sparclite this signal is low - active; in the v832 mode, it is high - active)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 31 specifications rev. 1.1 coral can be connected to the hitachi sh4 (sh7750), sh3 (sh7709) nec v832 and fujitsu sparclite (mb86833) without external circuit . in the sra m interface mode, coral can be used with any other cpu as well. the host cpu is specified by the mode0 to 2 pins. mode 2 mode 1 mode 0 cpu l l l sh3 l l h sh4 l h l v832 l h h sparclite h x x reserved when the bus cycle terminates, a ready signal l evel can be set . when using the rdy_ mode signal at ? high ? level , set two cycles as the cpu software wait of the cpu. (when bs_mode = ? high ? level, set the cpu software wait to three cycles.) rdy _ mode ready signal mode l when the bus cycle terminate s , s ets the xrdy signal to the ?not ready? level. h when the bus cycle terminates, sets the xrdy signal to the ?ready? level. a cpu with no bs (bus start) pin can be used. setting can be performed in all cpu modes. connection can be made to a cpu with no b s signa l by setting the bs_mode signal to ? high ? level. when not using the bs signal, fix the bs pin of coral at ? high ? level. when using the bs_mode signal as ? high ? level in the normally ready mode, set the cpu software wait to three cycles. bs _ mode bs signal mode l connect to a cpu with the bs signal h connect to a cpu without the bs signal the data signal is 32 bits (fixed). the address signal is 32 bits (per one double - word) 24 , and has a 64 - mbyte address field. (16 - mbyte address space is provid ed for v832 and sparclite.) the external bus operating frequency is up to 100 mhz. in the sh4, v832, and sparclite modes, when the xrdy signal is low, it is in the ready state. however, in the sh3 mode, when the xrdy signal is low, it is in the wait state . this signal is a tri - state output that is synchronized with the rising edge of bclki. dma data transfer is supported using an external dma controller. an interrupt signal is generated to the host cpu. the xrst input must be kept low for at least 300 s after setting the s (pll reset) signal to high. in the v832 mode, coral signals are connected to the v832 cpu as follows: coral pins v832 signals a24 xmwr dtack xtc drack dmaak
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 32 specifications rev. 1.1 2.3.2 video output i nterface table 2 - 2 video output interface pins pin name i/ o description dclko output dot clock signal for display dclki input dot clock signal input hsync i/o horizontal sync signal output horizontal sync input < in external sync mode > vsync i/o vertical sync signal output vertical sync input < in external sync mode > csync output composite sync signal output dispe output display enable period signal gv output graphics/video switch r 2 - 7 output d i gital picture (r) output g 2 - 7 output d i gital picture (g) output b 2 - 7 output d i gital picture (b) output xrgben in put signal to switch between rgb1 and 0 output/memory bus (md 63 to 58) 6 - bit display data is output as standard for r, g, and b. depending on the condition, 8 - bit display data can also be output for r, g, and b. fixing xrgben at 0, r0, 1, g0, 1, and b 0, 1 can be output to md62, 63, md60, 61, and md58, 59 respectively. when 8 - bit output is selected for r, g, and b, only the 32 - bit mode can be used for the memory bus width mode. additional setting of external circuits can generate composite video signal . synchronous to external video signal display can be performed. either mode which is synchronous to dclki signal or one which is synchronous to dot clock, as for normal display can be selected. since hsync and vsync signals are set to input state after re set , these signals must be pulled up lsi externally. the gv signal switches graphics and video at chroma key operation. when video is selected, the ?l ow ? level is output.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 33 specifications rev. 1.1 2.3.3 graphics memory interface table 2 - 3 graphics memory interface pins pin n ame i/o description md0 to 57 i/o graphics memory bus data md58 to 63/rgb i/o graphics memory bus data or rgb0 to 1 output ma0 to 14 output graphics memory bus data mras output row address strobe mcas output column address strobe mwe output write ena ble mdqm0 to 7 output data mask mclk0 output graphics memory clock output mclk1 input graphics memory clock input connect the interface to the external memory used as memory for image data. the interface can be connected to 64 - /128 - /256 - mbit sdram ( 1 6 - or 32 - bit length data bus ) without using any external circuit. 64 bits or 32 bits can be selected for the memory bus data. when 32 - bit memory bus data is used and 6 - bit output is used for r, g, and b (xrgben pin = 1), set md32 to 63 and mdqm4 to 7 to t he open state. when 32 - bit memory bus data is used and 8 - bit output is used for r, g, and b (xrgben pin = 0), set md32 to 39 to ?h igh ? level input and set md40 to 57 and mdqm4 to 7 to the open state. connect mclki to mclk0. when xrgben is fixed at ? 1 ? , md 58 to 63 can be used as graphics memory bus data. when xrgben is fixed at ? 0 ? , md58 to 63 can be used as digital rgb0 to 1 outputs.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 34 specifications rev. 1.1 2.3.4 clock input table 2 - 4 clock input pin s pin name i/o description clk input clock input signal s input pll reset signal ckm input clock mode signal clksel [1:0] input clock rate select signal inputs source clock for internal operation clock and display dot clock. normally, 4 fsc (= 14.31818 mhz: ntsc) is input. an internal pll generates the internal operation clock of 1 66 mhz/133 mhz and the display base clock of 4 00 mhz. ckm clock mode l output from internal pll selected h host cpu bus clock (bclk1) selected when ckm = l, selects input clock frequency when built - in pll used according to setting of clksel pins clks el1 clksel 0 input clock frequency multiplication rate display reference clock l l inputs 13.5 - mhz clock frequency 29 391.5 mhz l h inputs 14.32 - mhz clock frequency 28 400.96 mhz h l inputs 17.73 - mhz clock frequency 22 390.06 mhz h h reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 35 specifications rev. 1.1 2.3.5 test pin s table 2 - 5 test pin s pin name i/o description testh input input 3.3 - v power. trst input this is the test reset signal. before performing reset via s/xrst, perform reset via this signal (trst). 2.3.6 reset sequence see section 10.3.2 .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 36 specifications rev. 1.1 3 procedure of the hardware initialization 3.1 hardware reset 1.do the hardware reset. (see section 11.3.2) 2.after the hardware reset, set the ccf(change of frequency) register (section 9.2.1). in being unstable cycle after the hardware reset, keep 32 bus cycles open. 3.set the graphics memory interface register, mmr (memory i/f mode register). after setting the ccf register, take 200 us to set the mmr register. in being unstable memory access cycle, keep 32 bus cycles open. 4.other registers, except for the ccf re gister and the mmr register, should be set after setting the ccf register. in case of not using memory access, the mmr register could be set in any order after the ccf register is set. 3.2 re - reset 1. reset xrst signal. 2. see section 3.1 for registers setting after the procedure of re - reset. 3.3 software reset 1. set the value of the srst register (see section 9.2.1) for re - reset. 2. it is not necessary to reset the ccf register and the mmr register again.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 37 specifications rev. 1.1 4 host interface 4.1 operation mode 4.1.1 host cpu m ode select the host cpu by setting the mode0 to mode 2 signals as follows: table 4 - 1 cpu type setting mode 2 mode 1 mode 0 cpu l l l sh3 l l h sh4 l h l v832 l h h sparclite h x x reserved 4.1.2 ready s ignal m ode the mode2 pin can be used to set the ready si gnal level when the bus cycle of the host cpu terminates. for the normally not ready mode, set the software wait to 0 or 1 cycle s . when using this device in the normal ly ready mode, set the software wait to 2 cycles. when using this device in the normal ly not ready mode, set the software wait to one cycle. (when bs_mode = h , three cycles are needed for the software wait.) the ?normal ly not ready mode? is the mode in which the coral xrdy signal is always in the wait state and ready is returned only when read/write is ready. the ?normal ready mode? is the mode in which the coral xrdy signal is always in the ready state and it is put into the wait state only when read/write cannot be performed immediately. table 4 - 2 ready signal mode rdy _ mode ready signal operation l recognizes xrdy signal as ?not ready level? and terminates bus cycle (normal ly not ready mode) h recognizes xrdy signal as ?ready level? and terminates bus cycle (norma l l y ready mode)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 38 specifications rev. 1.1 4.1.3 bs signal mode connection to a cpu without the bs signal can be made via the bs_mode signal. this setting can be performed for all cpu modes. to connect to a cpu without the bs signal, set the bs_mode signal to ? high ? level. when not using the bs signal, fix the bs pin of coral at ? high ? level. when using the bs_mode signal as ? high ? level, with the normally ready mode established, set the cpu software wait to three cycles. table 4 - 3 bs signal mode bs _ mode operation of bs signal l connects to cpu with bs signal h connects to cpu without bs signal 4.1.4 endian c oral operates in little - endian mode. all the register address descriptions in the specifications are byte address in little endian. when using a big - endian cpu, note that the byte - or word - addresses are different from these descriptions.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 39 specifications rev. 1.1 4.2 access mode 4.2.1 sram i nterface data can be transferred to/from coral using sram access protocol. coral internal registers and graphics memory are all mapped to the physical address area of the host processor . coral uses hardware wait based on the xrdy signal, enabling the ha rdware wait setting of the host cpu. when using the normal ly not ready mode, set the software wait to ?1?. when using the normal ly ready mode, set the software wait to ?2?. (when using the bs_mode signal as ? high ? level, with the normally ready mode est ablished, set the cpu software wait to three cycles.) switch the ready mode using the rdy _ mode signal. cpu read the host processor reads data from internal registers and memory of coral in double - word (32 bit) units. valid data is output continuously whi le xrd and xcs are being asserted at a ?low? level after xrdy has been asserted. cpu write the host cpu writes data to internal registers and memory of coral in byte , word(16 bit) and double - word( 32 bit) units. 4.2.2 fifo i nterface (fixed transfer destination address) this interface transfers display lists stored in host memory. display list information is transferred efficiently using a single address mode dma transfer . data can be transferred to fifo in relation to fifo buffer area mapped in memory area usi ng sram interface or dual address mode .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 40 specifications rev. 1.1 4.3 dma transfer 4.3.1 data t ransfer u nit dma transfer is performed in double - word (32 bit s ) units or 8 double - word (32 byte s ) units. byte and word access is not supported. note: 8 double - word transfer is supported only in the sh4 mode. 4.3.2 address m ode dual address mode (mode using ack) dma is performed at memory - to - memory transfer between host memory and registers mapped in memory space or graphics memory (destination). both the host memory address and coral is used. in the sh4 mode, the 1 double - word transfer (32 bits) and 8 double - word transfer (32 bytes) can be used. when the cpu transfer destination address is fixed, data can also be transferred to the fifo interface. however, in this case, even the sh4 mode supports on ly the 1 double - word transfer. dreq and drack pins and sram interface signals are used. in v832, the dreq, dmaak, and xtc pins and sram interface signals are used. note: the sh3 mode supports the direct address mode; it does not support the indirect addre ss mode. dual address mode (mode not using ack) when not using the ack signal with the dual address mode established, set bit3 at hostbase+0004h (dna: dual address no ack mode) to 1. when the ack is not used, the dreq signal is in the edge mode and the dr eq signal is negated per transfer and then reasserted it in the next cycle. if processing cannot be performed immediately inside coral, the dreq signal remains negated. the transfer count register (dtc) of coral is not used, so in order to end dma transfe r, write ? 1 ? to the dma transfer stop register (dts) from the cpu. note 1: in the dual dma mode (mode without ack), the destination address can be used only for the fifo. in dma transfer to the graphics memory, etc., use the dual dma mode. note 2: dma read is not supported. single address mode (fifo interface) data is transferred between host memory (source) and fifo (destination). only the address output from the host memory is used , and the data is transferred to the fifo. this mode does not support dat a write to the host memory. when the fifo is full, the dma transfer is suspended. the 1 double - word transfer (32 bits) and the 8 double - word transfer (32 b ) can be used. dreq, dtack, and drack signal are used. note: the single - address mode is supported o nly in the sh4 mode.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 41 specifications rev. 1.1 4.3.3 bus m ode coral supports the dma transfer cycle steal mode and burst mode according to setting of external dma mode . cycle steal mode (in the v832 mode, the burst mode is called the single transfer mode.) in the cycle steal mode, the r ight to use the bus is obtained or released at every data transfer of 1 unit . the dma transfer unit can be selected from between the 1 double - word (32 bits) and 8 double - words (32 b). burst mode (in the v832 mode, the burst mode is called the demand trans fer mode.) when dma transfer is started, the right to use the bus is acquired and the transfer begins. the data transfer unit can be selected from between the 1 double - word (32 bits) and 8 double - words (32 b). note: when performing dma transfer in the dua l - address mode, a function for automatically negating dreq is provided based on the setting of the dbm register. 4.3.4 dma transfer r equest single - address mode dma is started when the coral issues an external request to dmac of the host processor. set the trans fer count in the transfer count register of the coral and then issue dreq. fix the cpu destination address to the fifo address. dual - address mode dma is started by two procedures: coral issues an external request to dmac of the host processor, or the cpu itself is started (auto request mode, etc.). i n ack use mode, s et the transfer count in the transfer count register of coral and then issue dreq. note: in the ack unused mode and t he v832 mode requires no setting of the transfer count register . 4.3.5 ending d ma t ransfer sh3/sh4 when the coral transfer count register is set to 0, dma transfer ends and dreq is negated. v832 when the xtc signal from the cpu is low - asserted while the dmaak signal to s coral is high - asserted, the end of dma transfer is recognized a nd dreq is negated. the end of dma transfer is detected in two ways: the dma status register (dst) is polled, and an interrupt to end the drawing command (fd000000 h ) is added to the display list and the interrupt is detected. in the dual address mode (mod e not using ack), the dma transfer count register (dtc) is not used, so the dma ending cannot be determined. the dreq signal can be negated to end dma by writing 1 from the cpu to the dma transfer stop register (dts) of coral at dma transfer end.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 42 specifications rev. 1.1 4.4 transfe r of local display list this is the mode in which the coral internal bus is used to transfer the display list stored in the graphics memory to the fifo interface. during transfer of the local display list, the host bus can be used for cpu read/write. how t o transfer list: store the display list in the local memory of coral, set the transfer source local address (lsa) and the transfer count (lco), and then issue a request (lreq). whether or not the local display list is currently being transferred is check ed using the local transfer status register (lsta). transfer path for local display list cpu sdram host if sdram memory if fifo internal bus cpu bus
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 43 specifications rev. 1.1 4.5 interrupt coral issues interrupt requests to the host cpu. following shows the types of interrupt factor and they can be enabled/disabled by imask (interrupt mask register). vertical synchronization detect field synchronization detect external synchronization error detect drawing command error drawing command execution end 4.6 sh3 mode in the sh3 mode, operation is as sured under the following conditi ons: normally not ready mode bclk (cpu bus clock) is 50 mhz or less . the xwait setup time is 9.0 ns or less . normally ready mode three cycles or more are set for the software wait. 4.7 wait software wait the software wait is a wait performed on the cpu sid e; this wait specifies how many cycles of the ready signal (xrdy) sampling timing is ignored. hardware wait the hardware wait is a wait on the coral side that occurs when coral itself cannot read/write data immediately.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 44 specifications rev. 1.1 4.8 memory map the following shows the memory map of coral to the host cpu memory space . the address is mapped differently in sh3, sh4 and v832. fig. 4 .1 memory map table 4 - 4 address space in sh3/sh4 mode size resource base address (name) 3 2 m b to 256 kb 00000000 64 kb host i nterface registers 01fc0000 (hostbase) 32 kb display registers 01fd0000 (displaybase) 32 kb drawing registers 01ff0000 (drawbase) 32 kb geometry engine registers 01ff8000 (geometrybase) 32 mb graphics memory 02000000 table 4 - 5 address space in v832 , sparclite mode size resource base address (name) 16 mb to 256 kb graphics memory 00000000 64 kb host interface registers 00fc0000 (hostbase) 32 kb display registers 00fd0000 (displaybase) 32 kb drawing registers 00ff0000 (drawbase) 32 kb geometry e ngine registers 00ff8000 (geometrybase) register area graphics memory area 32 mb to 256 kb 256 kb 0000000 to 1fbffff 1fc0000 to 1ffffff 2000000 to 3ffffff 64 mb space (sh3/sh4) register area 256 kb 0fcffff to 0ffffff 16 mb space (v832, sparclite) 32 mb 0000000 to 0fbffff gr aphics memory area graphics memory area 16 mb to 256 kb
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 45 specifications rev. 1.1 when the sh3 or sh4 mode is used, the register area can be moved by writing 1 to bit 0 at hostbase + 005ch (rsw: register location switch). in the initial state, the register space is at the center (1fc0000) of t he 64 mb space; access coral after about 20 bus clocks after writing 1 to rsw. fig. 4 . 2 memory map table 4 - 6 address mapping in sh3/sh4 mode size resource base address (name) 64 mb to 256 kb graphics memory 0 0000000 64 kb host interface registers 0 3f c0000 (hostbase) 32 kb display registers 0 3f d0000 (displaybase) 32 kb drawing registers 0 3f f0000 (drawbase) 32 kb geometry engine registers 0 3f f8000 (geometrybase) register area graphics memory area 32 mb to 256 kb 256 kb 0000000 to 1ffffff 3fc0000 to 3ffffff 2000000 to 3fbffff 64 mb space (sh3/sh4) 32 mb graphics memory area
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 46 specifications rev. 1.1 5 graphics memory 5.1 configuration the coral uses local external memory (graphi cs memory) for drawing and display management. the configuration of this graphics memory is described as follows: 5.1.1 data type the coral handles the following types of data. display list can be stored in the host (main) memory as well. texture/tile pattern a nd text pattern can be defined by a display list as well. drawing frame this is a rectangular image data field for 2d/3d drawing. the coral is able to have plural drawing frames and display a part of these area if it is set to be bigger than display size . the maximum size is 4096x4096 pixel in 32 pixel units. and both indirect color ( 8 bits / pixel) and direct color ( 16 bits / pixel) mode are applicable. display frame this is a rectangle picture area for display. the coral is able to set display layer up to 6 layers. z buffer z buffer is required for eliminating hidden surfaces. in 16 bits modes, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. this area has to be cleared before drawing. polygon drawing flag buffer this area is used fo r polygon drawing. it is required 1 bit memory area per 1 pixel and 1 x - axis line area both backward and forward of it. this area has to be cleared before drawing. displaylist buffer the displaylist is a list of drawing commands and parameters. texture p attern this pattern is used for texture mapping. the maximum size is up to 4096 x 4096 pixels. cursor pattern this is used for hardware cursor. the data format is indirect color ( 8 bits / pixel) mode. and the coral is able to display two cursor of 64 x 64 pixel size. frame buffer, z buffer, displaylist and etc by xrr size by drawing frame sizy by xrr size frame buffer, z buffer, displaylist and etc polygon drawing flag area => (y resolution + 2) * x resolution base address of polygon drawing buffe r(pfbr)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 47 specifications rev. 1.1 5.1.2 memory mapping a graphics memory is mapped linearly to host cpu address field. each of these above data is able to be allocated anywhere in the graphics memory according to the respective register setting. ( however there is some restric tions of an addressing boundary depending on a data type.) 5.1.3 data format direct color ( 16 bits / pixel ) this data format is described rgb as each 5 bit. bit15 is used for alpha bit of layer blending. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a r g b in direct color ( 8 bits / pixel ) this data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 0 color code z value it is possible to use z value as 8 bits or 16 bits. these data format are unsigned integer. 1 ) 16 bits mode 15 1 4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 unsigned integer 2 ) 8 bits mode 7 6 5 4 3 2 1 0 unsigned integer polygon drawing flag this data format is 1 bit per 1 pixel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 48 specifications rev. 1.1 texture / tile pattern it is possible to use a pattern as direct color mode ( 16 bits / pixel) or indirect color mode ( 8 bits / pixel ). 1 ) d irect color mode ( 16 bits / pixel) this data format is described rgb as each 5 bit. bit15 is used for alpha bit of stencil or stencil blending. ( only texture mapping) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a r g b 2) indirect color mode ( 8 b its / pixel) this data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 0 color code cursor pattern this data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 0 color code video capture data this da ta format is y:cb:cr=4:2:2 and 32 bits per 2 pixel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 y0 cb 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 y1 cr direct color ( 32 bits / pixel ) this data format is described rgb as each 8 bit. bit31 is used for alpha bit of layer blending. but the coral does not support this color mode drawing. therefore please draw this layer by cpu writing. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 g b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 a reserved r
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 49 specifications rev. 1.1 5.2 frame mana gement 5.2.1 single buffer the entire or partial area of the drawing frame is assigned as a display frame. the display field is scrolled by relocating the position of the display frame. when the display frame crosses the border of the drawing frame, the other side of the drawing frame is displayed, assuming that the drawing frame is rolled over (top and left edges assumed logically connected to bottom and right edges, respectively). to avoid the affect of drawing on display, the drawing data can be transferred to the graphics memory in the blanking time period. 5.2.2 double buffer two drawing frames are set. while one frame is displayed, drawing is done at the other frame. flicker - less animation can be performed by flipping these two frames back and forth. flippin g is done in the blanking time period. there are two flipping modes: automatically at every scan frame period, and by user control. the double buffer is assigned independently for the l2, l3, l4, l5 layers. 5.3 memory access 5.3.1 memory access by host cpu grap hics memory is mapped linearly to host cpu address field. the host cpu can access the graphics memory like a sram. 5.3.2 priority of memory accessing the priority of graphics memory accessing is the follows: 1. refresh 2. display processing 3. host cpu accessing 4. drawin g accessing
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 50 specifications rev. 1.1 5.4 connection with memory 5.4.1 connection with memory the memory controller of coral supports simple connection with sd/fcram by setting mmr(memory mode register). if there is n(=11 to 13) address pins in sd/fcram, please connect the sd/fcram addr ess(a[n]) pin to the coral ? s memory address(ma[n] ) pin and sd/fcram bank pin to the coral ? s next address(ma[n]) pin. then please set mmr by a number and type of memory. the follows are the connection table between coral pin and sd/fcram pin. 64m bit sdra m(x16 bit) 64m bit sdram(x32 bit) coral pins sdram pins coral pins sdram pins ma[11:0] a[11:0] ma[10:0] a[10:0] ma12 ba0 ma11 ba0 ma13 ba1 ma12 ba1 128m bit sdram(x16 bit) 128m bit sdram(x32 bit) cor al pins sdram pins coral pins sdram pins ma[11:0] a[11:0] ma[11:0] a[11:0] ma12 ba0 ma12 ba0 ma13 ba1 ma13 ba1 256m bit sdram(x16 bit) 16m bit fcram(x16 bit) coral pins sdram pins coral pins fcram pins ma[12:0] a[12:0] m a[10:0] a[10:0] ma13 ba0 ma11 ba ma14 ba1
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 51 specifications rev. 1.1
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 52 specifications rev. 1.1 6 display controller 6.1 overview display control window display can be performed for six layers. window scrolling, etc. , can also be performed. back ward compatibility back ward compatibility with previous products is supported in the four - layer display mode or in the left/right split display mode. video timing generator the video display timing is generated according to the display resolution (from 320 240 to 1024 768). color look - up there are two sets of color look - up tables by palette ram for the indirect color mode (8 bits/pixel). cursor two sets of hardware cursor patterns (8 bits/pixel, 64 64 pixels each) can be used. 6.2 display function 6.2.1 layer configuration six - layer window display is performed. lay er overlay sequence can be set in any order. a four - layer display mode and left/right split display mode are also provided, supporting backward compatibility with previous products. l0 ( l0wx,l0wy ) l2 ( l2wx,l2wy ) l1 ( l1wx,l1wy ) l5 ( l5wx,l5wy ) l4 ( l4wx,l4wy ) l3 ( l3wx,l3wy ) (a) six layerd window display l0,l2,l4 ( 0,0 ) l3,l5 ( hdb+1 , 0 ) l1 ( wx,wy ) (b) four la yered display for downward compatibility background color
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 53 specifications rev. 1.1 configuration of display layers the correspondence betw een the display layers for this product and for previous products is shown below. coordinates of starting point width/height layer correspondence window mode compatibility mode window mode compatibility mode l0 c (l0wx, l0wy) (0, 0) (l0ww, l0wh + 1) (hd p + 1, vdp + 1) l1 w (l1wx, l1wy) (wx, wy) (l1ww, l1wh + 1) (ww, wh + 1) l2 ml (l2wx, l2wy) (0, 0) (l2ww, l2wh + 1) (hdb + 1, vdp + 1) l3 mr (l3wx, l3wy) (hdb, 0) (l3ww, l3wh + 1) (hdp - hdb, vdp + 1) l4 bl (l4wx, l4wy) (0, 0) (l4ww, l4wh + 1) (hdb + 1 , vdp + 1) l5 br (l5wx, l5wy) (hdb, 0) (l5ww, l5wh + 1) (hdp - hdb, vdp + 1) c, w, ml, mr, bl, and br above mean layers for previous products. the window mode or the compatibility mode can be selected for ea ch layer. it is possible to use new functions through minor program changes by allowing the coexistence of display modes instead of separating them completely. however, if high resolutions are displayed, the count of layers that can be displayed simultaneously and pixel data may be restricted accord ing to the graphics memory ability to supply data.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 54 specifications rev. 1.1 6.2.2 overlay (1) overview image data for the six layers (l0 to l5) is processed as shown below. the fundamental flow is : palette ? layer selection ? blending. the palettes convert 8 - bit c olor codes to the rgb format. the layer selector exchanges the layer overlay sequence arbitrarily. the blender performs blending using the blend coefficient defined for each layer or overlays in accordance with the transparent - color definition. the l0 la yer corresponds to the c layer for previous products and shares the palettes with the cursor. as a result, the l0 layer and cursor are overlaid before blend operation. the l1 layer corresponds to the w layer for previous products. to implement back ward co mpatibility with previous products, the l1 layer and lower layers are overlaid before blend operation. the l2 to l5 layers have two paths; in one path, these layers are input to the blender separately and in the other, these layers and the l1 layer are ove rlaid and then are input to the blender. when performing processing using the extended mode, select the former; when performing the same processing as previous products, select the latter. it is possible to specify which one to select for each layer. pallet - 1 yuv/rgb pallet - 2 pallet - 3 pallet - 0 layer selector l0(c) data l2(ml) data cursor0 data l2 data l3 data l4 data l5 data blender overlay cursor1 data l1(w) data l4(bl) data l3(mr) data l5(br) data
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 55 specifications rev. 1.1 (2 ) overlay mode image layer overlay is performed in two modes: simple priority mode , and blend mode. in the simple priority mode, processing is performed according to the transparent color defined for each layer. when the color is a transparent color, th e value of the lower layer is used as the image value for the next stage; when the color is not a transparent color, the value of the layer is used as the image value for the next stage. d view = d new (when d new does not match transparent color) = d lower ( when d new matches transparent color) when the l1 layer is in the ycbcr mode, transparent color checking is not performed for the l1 layer; processing is always performed assuming that transparent color is not used. in the blend mode, the blend ratio ? r ? defined for each layer is specified using 8 - bit tolerance, and the following operation is performed: d view = d new *r + d lower* (1 ? r) blending is enabled for each layer by mode setting and a specific bit of the pixel is set to ? 1 ? . for 8 bits/pixel, the msb of ram data enable s blending; for 16 bits/pixel, the msb of data of the relevant layer enable s blending; for 24 bits/pixel, the msb of the word enable s blending. (3) blend coefficient layer in the normal blend mode, the blend coefficient is fixed for each layer. however , in the blend coefficient layer mode, the l5 layer can be used as the blend coefficient layer. in this mode, the blend coefficient can be specified for each pixel, providing gradation, for example. when using this mode, set the l5 la yer(l5m and l5em register) to 8 bits/pixel, window display mode and extend overlay mode.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 56 specifications rev. 1.1 6.2.3 display p arameters the display area is defined according to the following parameters. each parameter is set independently at the respective register. fig. 5 .1 display parameters note: the actual parameter settings are little different from the above. the details, please refer ? 11.3.1 interlaced mode ? . htp horizontal total pixels hsp horizontal synchronize pulse position hsw horizontal synchronize p ulse width hdp horizontal display period hdb horizontal display boundary vtr vertical total raster vsp vertical synchronize pulse position vsw vertical synchronize pulse width vdp vertical display period ln wx layer n window position x ln wy layer n window position y ln ww layer n window width ln wh layer n window height when not splitting the window , set hdp to hdb and display only the left side of the window . the settings must meet the following relationship: 0 < hdb hdp < hsp < hsp + hsw + 1 < htp 0 < vdp < vsp < vsp + vsw + 1 < vtr htp h s p h db h dp ln wy ln wx ln ww ln wh v dp v s p v tr v sw h sw
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 57 specifications rev. 1.1 6.2.4 display p osition c ontrol the graphic image data to be displayed is located in the logical 2d coordinate s space (logical graphics space ) in the graphics memory. there are six logical graphics spaces as follows: l0 l ayer l1 layer l2 layer l3 layer l4 layer l5 layer the relation between the logical graphics space and display position is defined as follows: fig. 5 .2 display position parameters oa origin address origin address of logical graphics space . memory address of top left edge pixel in logical frame origin w stride width of logical graphics space . defined in 64 - byte unit h height height of logical graphics space . total raster (pixel) count of field da display address display origin address . top left position address of display frame origin dx dy display position display origin coordinate s . coordinate s in logical frame space of display frame origin stride (w) height (h) origin address (oa) display address (da) display position x,y ( dx , dy ) v dp logical frame display frame h dp
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 58 specifications rev. 1.1 coral scans the logical graphics space as if the entire space is rolled over in both the h orizontal and vertical directions. using this function, if the display frame crosses the border of the logical graphics space , the part outside the border is covered with the other side of the logical graphics space , which is assumed to be connected cycli cally as shown below: fig. 5 .3 wrap around of display frame the expression of the x and y coordinates in the frame and their corresponding linear addresses (in bytes) is shown below. a(x,y) = x bpp/8 + 64wy (bpp = 8 or 16) the origin of t he displayed coordinates has to be within the frame. to be more specific, the parameters are subject to the following constraints: 0 dx < w 64 8/bpp (bpp = 8 or 16) 0 dy < h dx, dy, and da have to indicate the same point within the frame. in sho rt , the following relationship must be satisfied . da = oa + dx bpp/8 + 64w dy (bpp = 8 or 16) 64 w l logical frame o rigin additionally drawn area new display origin previo u s display origin
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 59 specifications rev. 1.1 6.3 display color color data is displayed in the following modes: indirect color (8 bits/pixel) in this mode, the index of the palette ram is displayed. data i s converted to image data consisting of 6 bits for r, g, and b via the palette ram and is then displayed. direct color (16 bits/pixel) each level of r, g, and b is represented using 5 bits. direct color (24 bits/pixel) each level of r, g, and b is represen ted using 8 bits. ycbcr color (16 bits/pixel) in this mode, image data is displayed with ycbcr = 4:2:2. data is converted to image data consisting of 8 bits for r, g, and b using the operation circuit and is then displayed. the display color s for each la yer are shown below. layer compatibility mode extended mode l0 direct color (16, 24), indirect color (p0) direct color (16, 24), indirect color (p0) l1 direct color (16, 24), indirect color (p1), ycbcr direct color (16, 24), indirect color (p1), ycbcr l2 direct color (16, 24), indirect color (p1) direct color (16, 24), indirect color (p2) l3 direct color (16, 24), indirect color (p1) direct color (16, 24), indirect color (p3) l4 direct color (16, 24), indirect color (p1) direct color (16, 24) l5 dire ct color (16, 24), indirect color (p1) direct color (16, 24) ? pn ? stands for the corresponding palette ram. four palettes are used as follow s : palette 0 (p0) this palette corresponds to the c - layer palette for previous products. this palette is used fo r the l0 layer. this palette can also be used for the cursor. palette 1 (p1) this palette corresponds to the m/b layer palette for previous products. in the compatibility mode, this palette is common to layers l1 to 5. in the extended mode, this palette is dedicated to the l1 layer. palette 2 (p2) this palette is dedicated to the l2 layer. this palette can be used only for the extended mode. palette 3 (p3) this palette is dedicated to the l2 layer. this palette can be used only for the extended mode.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 60 specifications rev. 1.1 6.4 cursor 6.4.1 cursor d isplay function coral can display two hardware cursors. each cursor is specified as 64 64 pixels, and the cursor pattern is set in the graphics memory. the indirect color mode (8 bits/pixel) is used and the l0 layer palette is used. how ever, transparent color control ( handling of transparent color code and code 0) is independent of l0 layer . blending with lower layer is not performed. 6.4.2 cursor control the display priority for hardware cursors is programmable. the cursor can be displayed either on upper or lower the l0 layer using this feature. a separate setting can be made for each hardware cursor. if part of a hardware cursor crosses the display frame border, the part outside the border is not shown. usually, cursor 0 is preferred to cursor 1. however, with cursor 1 displayed upper the l0 layer and cursor 0 displayed lower the l0 layer, the cursor 1 display is preferred to the cursor 0.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 61 specifications rev. 1.1 6.5 display scan control 6.5.1 applicable d isplay the following table shows typical display resolutions and their synchronous signal frequencies. the pixel clock frequency is determined by setting the division rate of the display reference clock. the display reference clock is either the internal pll (400. 9 mhz at input frequency of 14.318 mhz), or the clock s upplied to the dclki input pin. the following table gives the clock division rate used when the internal pll is the display reference clock: table 4 - 1 resolution and display f requency resolution division rate of reference clock pixel frequency horizontal total pixel count horizontal frequency vertical total raster count vertical frequency 320 240 1/ 6 0 6.7 mhz 424 15.76 khz 263 59.9 hz 400 240 1/ 48 8.4 mhz 530 15.76 khz 263 59.9 hz 480 240 1/ 4 0 10.0 mhz 636 15.76 khz 263 59.9 hz 640 480 1/ 16 25 .1 mhz 800 31.5 khz 525 59.7 hz 854 480 1/ 12 33.4 mhz 1062 31.3 khz 525 59.9 hz 800 600 1/10 40.1 mhz 1056 38.0 khz 633 60.0 hz 1024 768 1/6 66.8 mhz 1389 48.1 khz 806 59.9 hz pixel frequency = 14.318 mhz 28 reference clock division rate (wh en internal pll selected) = dclki input frequency reference clock division rate (when dclki selected) horizontal frequency = pixel frequency/horizontal total pixel count vertical frequency = horizontal frequency/vertical total raster count
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 62 specifications rev. 1.1 6.5.2 interlace d i splay coral can perform both a non - interlace display and an interlace display. when the dcm register synchronization mode is set to interlace video (11), images in memory are output in odd and even rasters alternately to each field, and one frame (odd + ev en fields) forms one screen. when the dcm register synchronization mode is set to interlace (10), images in memory are output in raster order. the same image data is output to odd fields and even fields. consequently, the count of rasters on the screen i s half of that of interlace video. however, unlike the non - interlace mode, there is a distinction between odd and even fields depending on the phase relationship between the horizontal and vertical synchronous signal s . fig. 5.4 display differ ence between synchronization modes odd eve n non - interlace interlace video interlace
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 63 specifications rev. 1.1 6.6 the external synchronous signal the display scan can be performed by synchronizing horizontal/vertical synchronous signal from the external. in selecting the external synchronization mode, coral is sampling the hsync si gnal and displays the synchronizing the external video signal. either the internal pll clock or the dclki input signal could be selected for the sampling clock. also, the superimposed analog output is performed by the chroma key process. the following d iagram shows an example of the external synchronization circuit. h sync vsync coral video sw digital rgb out analo g rgb in superimposed analog rgb out hsync in vsync in gv (pedestal clump input) compare 3 states keyc external s ync enable hsync out vsync out c ursor 0 c ursor 1 l0 buffer register ckm bit esy bit display timming generator overlap dac d - ffs latency compensation for dac l0 l1 l2 l3 l4 l5 an example of the external synchronization circuit the external synchronization mode is performed by setting the esy bit of the dcm register. in setting the extern al synchronization mode, hsync, vsync, and eo pin of coral is changed to the input mode. after that it needs to be provided the synchronous signal by using the 3 state buffer from the external. when turning off the external synchronization mode, coral in ternal esy bit needs to be switched off after disconnecting the synchronous input signal from the external. the buffer of the external synchronization signal must not be switched on when the synchronous output signal of coral is on. follow the previous in struction to prevent simultaneous on from occurring. in using the external synchronous signal with the display clock based on the internal pll, coral extends the clock period and fits the clock phase with the horizontal synchronous signal phase after inpu tting the horizontal synchronous pulse. the following caution is necessary. in case of connecting the high speed transmit signal, such as lvds, with the digital rgb output, pll with a built - in the high speed serial transmission is temporally unstable due to this connection. therefore,
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 64 specifications rev. 1.1 the external synchronous signal based on the internal pll must not be used with high speed synchronous transmit signal. the synchronization of the horizontal direction is controlled by the following state diagram. disp sync the horizontal resolution counter = hdp otherwise otherwise otherw ise when the horizontal resolution counter matches the htp, it is initialized. detecting the external horizontal synchronous signal or the horizontal synchronous pulse counter = hsw otherwise the horizontal resolution counter is is halted, starts to count the horizontal synchronous pulse counter. fporch bporch the horizontal resolution counter = hsp the horizontal resolution counter = htp the finite state diagram is controlled by the horizontal resolution counter. the period of outputting the signal is assigned the disp state. when the value of the horizontal resolution counter matches that of the hdp register, it ends t o output the signal and the current state is transmitted from disp state to fporch state (front porch). in the fporch state, when the value of the vertical resolution register matches that of the hsp register, the current state is transmitted to the sync state. in this state, it waits for the horizontal synchronous signal from the external. coral detects the negative edge of the horizontal synchronous pulse from the external and synchronizes it. in detecting the horizontal synchronous signal from the ex ternal, the current state is transmitted to the bporch state (back porch). the horizontal resolution register does not count in the sync state, instead the horizontal synchronous counter is incremented from zero. when the value of this counter matches th e setting value of the hsw register, the current state is transmitted to the bporch state without detecting the horizontal synchronous signal form the external. when the value of the horizontal resolution counter matches that of the htp register in the bp orch state, the horizontal resolution counter is reset, and also the current state is transmitted to the disp state and it begins to display the next cluster.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 65 specifications rev. 1.1 the synchronization of vertical direction is controlled by the following state diagra m. the cluster counter = vtr disp the cluster counte r = vdp otherwise otherwise otherwise when the cluster counter matches the vtp, it is initialized. detecting the negative edge of the external vertical synchronous pulse otherwise detecting the external vertical synchronous pulse to be asserted fporch bporch sync the state diagram of the vertical direction is controlled by the value of the cluster counter. the period of outputting the signal is assigned the disp state. when the value of the cluster counter matches the value of the vdp register, it ends to output the signal and the current state is transmitted from the disp state to the fporch state. in the fporch state, it waits the external synchronous pulse to be asserted. in detecting the external synchronous pulse to be asserted, the current state is transmitted to the sync state. in the sync state, it waits for the negative edge of the external synchronous signal. in detecting the negative edge, the current state is transmitted to the bporch state. when the value of the cluste r counter matches the values of the vtr register, the cluster counter is reset, and also the current state is transmitted to the disp state and it starts to display the next field.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 66 specifications rev. 1.1 6.7 video interface, ntsc/pal output in outputting ntsc sig nal, ntsc/pal encoder must be connected externally as shown below: fig. 5.4 example of ntsc encoder connection the digital ntsc encoder can also be used, but in general, the usable pixel frequency/resolution are limited. for details, refer to the specifications for each company ? s digital ntsc encoder. c sync r7 - 2 , md63 - 61 coral mb3516a video - out g7 - 2 , md60 - 58 b7 - 2 , md 57 - 55 dclko csync - in r - in g - in b - in fsc - in dac rout gout bout r7 - 0 g7 - 0 b7 - 0 clk 1 / 4 c lk 14.318 mhz xrgben
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 67 specifications rev. 1.1 7 geometry engine 7.1 geometry pipeline 7.1.1 processing f low the flow of geometry is shown below. object coordinates (oc) clip coordinates (cc) normalized device coordinates (ndc) drawing (device) coordinates (dc) mvp t ransformation clipping 3d - 2d t ransformation view port transformation back face carling
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 68 specifications rev. 1.1 7.1.2 model - v iew - p rojection (mvp) t ransformation (oc ? cc c oordinate t ransformation) the geometry engine transforms the vertex of the ?oc? coordinate system specified by the g_vertex packet to the ?cc? coordinate system according to the coordinate transformation matrix (oc ? cc matrix) specified by the g_loadmatrix packet. the ?oc ? cc m atrix? is a ?4 4? matrix consisting of a modelview matrix and a projection matrix. if ?zoc? is not contained in the input parameter of the g_vertex packet (z - bit of gmdr0 is off), (oc ? cc) coordinate transformation is processed as ?zoc = 0?. when gmdr0[ 0] is 0 (orthogonal projection transformation), oc ? cc coordinate transformation is processed as ?wcc = 1.0?. oc: object coordinates cc: clip coordinates ma0 to md3: oc ? cc matrix xoc to zoc: x, y, and z of oc coordinate system xcc to woc: x, y, z, and w of cc coordinate system 7.1.3 3d - 2d transformation (cc ? ndc c oordinate t ransformation) the geometry engine divides ?xyz? of the ?cc? coordinate system by ?wcc? (perspective division). ndc: normalized device coordinates xndc to zndc: x, y, and z of ?ndc? coordinate system ma0 mb0 mc0 md0 ma1 mb1 mc1 md1 ma2 mb2 mc2 md2 ma3 mb3 mc3 md3 xcc ycc zcc wcc xoc yoc zoc 1 = xndc yndc zndc = 1/wcc xcc ycc zcc
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 69 specifications rev. 1.1 7.1.4 view p ort t ransformation (ndc ? dc c oordinate t ransformation) the geometry engine transforms ?xyz? of the ?ndc? coordinate system to the ?dc? coordinate system according to the transformation coefficient specified by g_viewport and g_depthrange. ?x_scaling,x_offset? and ?y_scaling,y_offset? are coefficients to be mapped finally to frame buffer. xdc and ydc must be included within the drawing input range ( - 4096 to 4095). ?z_scaling? and ?z_offset? are coefficients to be mapped finally to ?z buffer?. ?zdc? must be included within the ?z buffer? range (0 to 65535). dc: device coordinates xdc = x_scaling*xndc + x_offset ydc = y_scaling*yndc + y_offset zdc = z_scaling*zndc + z_offset 7.1.5 view v olume c lipping expression for determinat ion the expression for determining the coral view volume clipping is shown below. w clipping is intended to prevent the overflow caused by 1/w. xmin*wcc xcc xmax*wcc ymin*wcc ycc ymax*wcc zmin*wcc zcc zmax*wcc wmin wcc note: xmin, xmax, ym in, ymax, zmin, zmax, and wmin are the clip boundary values set by the g_viewvolumexyclip/zclip/wclip packet. clipping - on/ - off view volume clipping - on/ - off can be switched by using the clip boundary values set by the g_viewvolumexyclip/zclip/wclip packet. to switch view volume clipping to off, set the maximum and minimum values of the geometry data format (ieee single - precision floating point(*1)) in the ?clip.max? value(*2) and ?clip.min? value(*3), respectively. in this case, ?all coordinate transformat ion results? can be evaluated as within view volume range , making it possible to obtain the effect of view volume clipping - off. this method is valid only when w clipping does not occur . when a clip boundary value (wmin) that causes w clipping to occur is set, clipping is also performed for each clip area. consequently, set an appropriate clip boundary value for clip. max value. and clip. min value . , respectively. if other values are set in ?clip.max? and clip.min, view volume clipping - on operates. the co ordinate transformation result is always compared with the values set in ?clip.max? and ?clip.min?. *1: maximum value = 0x7f7fff f f, minimum value = 0xff7fff f f *2: xmin,ymin, zmin, wmin *3: xmax, ymax, zmax
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 70 specifications rev. 1.1 an example of the g_viewvolumezclip packet is shown below. 0xf1012010 //setting of gmdr0 0x00000000 //data format: floating point data format 0x45000000 //g_viewvolumezclip packet 0xff7ffff f //zmin.float setting value (minimum value of ieee single - precision floating point) 0x7f7f f fff //zmax.float setting value (maximum value of ieee single - precision floating point) example of g_viewvolumezclip packet when z clipping off ?w? clipping at orthogonal projection transformation ?w? at orthogonal projection transformation (gmdr0[0] = 0) is treated as ?w cc=1.0?. for this reason, to suppress ?w? clipping, the set ?wmin? value must be larger than 0 and 1.0 or less. relationship with drawing clip frame for the following reasons, the clip boundary values of the view volume should be set so that the values af ter dc coordinate transformation will be larger than the drawing clip frame (2 pixels or more). (1) ?xy? on the view volume clip frame of the ?cc? coordinate system may be drawn one pixel outside or inside the frame due to an operation error when it is fin ally mapped to the ?dc? coordinate system. (2) when the end point of a line overlaps the view volume frame mapped to the ?dc? coordinate system, there are two cases, where the dots on the frame are drawn, and not drawn depending on the specifying of the li ne drawing attribute (end point drawing/non - drawing). (3) when the start point of a line overlaps the view volume frame mapped to the ?dc? coordinate system, the dots on the frame are always drawn. when the line drawing attribute is ?end point non - drawing ,? the dots on the frame are drawn at the starting point, but they may not be drawn at the end point. (4) when applying to triangle and polygon drawing the rasterizing rule ?dots containing center of pixel drawn. dots on right side and base of triangle no t drawn.? depending on the value of the fraction, a gap may be produced between the right side and base of the frame. drawing clip frame drawing area a space of two pixels or more is required . ? dc ? c oordinates image of view volume clip frame
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 71 specifications rev. 1.1 7.1.6 back face c u rling in coral , a triangle direction can be defined and a mode in which drawing for the back face is inhibited (back face carling) is supported. the on/off operation is controlled by the gmdr2[0] setting. gmdr2[0] must be set to 1 only when back face carling is required. when back face carling is not required such as in ?line,? ?point,? and ?polygon primitive,? gmdr2 [0] must be set to 0.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 72 specifications rev. 1.1 7.2 data format 7.2.1 data format the supported data formats are 32 - bit single - precision floating - point format, 32 - bit fixed - point format, integer packed format, and rgb packed format. all internal processing is performed in the floating - poi nt format. for this reason, the integer packed format, fixed - point format, and rgb packed format must be converted to the floating - point format. the processing speeds in these formats are slightly lower than in the 32 - bit single - precision floating - point format. the data format to use is selected by setting the gmdr0 register. (1) 32 - bit single - precision floating - point format 31 30 23 22 0 s e f s: sign bit (1 bit) e: exponent part (8 bits) f: mantissa (23 bits) : ?1.f? show s the fraction. ?1? is a hidden bit. the numerical value of the floating - point format becomes ( - 1) s (1.f)2 (e - 127) (0 < e < 255). (2) signed fixed - point format (sfix16.16) 31 30 16 15 0 s int frac s: sign bit (1 bit) int: int eger (15 bits) frac: fraction (16 bits) (3) signed integer packed format (sint16.sint16) 31 30 16 15 14 0 s y.int s x.int s: sign bit (1 bit) int: integer (15 bits) (4) rgb packed format 31 24 23 16 15 8 7 0 reserved r g b r, g, b: color bits (8 bits) ( 5 ) a rgb packed format 31 24 23 16 15 8 7 0 a r g b a : alpha bits (8 bits) r, g, b: color bits (8 bits)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 73 specifications rev. 1.1 7.3 setup engine 7.3.1 setup processing the vertex data transformed by the g eometry engine is transferred to the setup engine. coral has a drawing interface that is compatible with the mb86290a. it operates parameters for various slope calculations, etc., with the setup engine. when the obtained parameters are set in the drawin g engine, the final drawing processing starts. 7.4 log output of device coordinates a function is provided to output device coordinates (dc) data obtained by view port conversion to local memory (graphics memory). 7.4.1 log output mode drawing & log output comman d log output of drawing coordinates (device coordinates) can be performed concurrently with primitive drawing. log output can be controlled using the command with log output on/off attribute; log output is performed only when the log output on attribute is specified. log output dedicated command when the log output dedicated command is used, log output of the device coordinates can be performed. 7.4.2 log output destination address the log output destination address is controlled by the device coordinates log poi nter. once set an address, this pointer automatically increment an output address.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 74 specifications rev. 1.1 8 drawing processing 8.1 coordinate system 8.1.1 drawing coordinate s after the calculation of coordinates by the geometry engine, coral draws data in the drawing frame in the graphics memory that finally uses the drawing coordinates (device coordinates). drawing frame is treated as 2d coordinate s with the origin at the top left as shown in the figure below . the maximum coordinate s is 4096 4096. each drawing frame is located in the graphics memory by setting the address of the origin and resolution of x direction (size ). although the size of y direction does not need to be set , y coordinates which are max. at drawing must not be overlapped with other area . in addition , at drawing, specifying the clip frame (top left and bottom right coordinates) can prevent the drawing of images outside the clip frame . x (max. 4096 ) y (max. 4096) origin drawing frame size x drawing frame size y (xmin, ymin) (xmax, ymax) clip frame
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 75 specifications rev. 1.1 8.1.2 texture c oordinate s texture coordinate is a 2d coordinate system represented as s and t (s: horizontal, t: vertical). a ny integer in a range of - 8192 to + 8191 can be used as the s and t coordinates. the texture coordinate s is correlated to the 2d coordinate s of a vertex. one texture pattern can be applied to up to 4096 4096 pixels. the pattern size is set in the regis ter. when the s and t coordinate s exceed the maximum pattern size, the repeat, cramp or border color option is selected. s (max. 8192) t (max. 8192) origin max. 4096 pixels max. 4096 pixels texture pattern
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 76 specifications rev. 1.1 8.1.3 frame b uffer for drawing, the following area must be assigned to the graphics memory. the frame size ( count of pixels on x direction ) is common for these areas. drawing frame the results of drawing are stored in the graphical image data area. both the direct and indirect color mode are applicable. z buffer z buffer is required for eliminating hidden surfaces . in 16 bits mo de, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. polygon draw ing flag buffer this area is used for polygon drawing. 1 bit is required per 1 pixel .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 77 specifications rev. 1.1 8.2 figure drawing 8.2.1 drawing p rimitives coral has a drawing interface that is compatible with the mb86290a graphics controller which does not perform geometry processing. the following types of figure drawing primitives are compatible with the mb86290a. point line triangle high - speed 2dline high - speed 2dtriangle polygo n 8.2.2 polygon d rawing function an i rregular polygon (including concave shape) is drawn by hardware in the following manner: 1. execute polygonbegin command. initialize polygon draw ing hardware. 2. draw vertices. draw outline of polygon and plot all vertices to polygon draw flag buffer usin g high - speed 2dtriangle primitive. 3. execute polygonend command. copy shape in polygon draw flag buffer to drawing frame and fill shape with color or specified tiling pattern.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 78 specifications rev. 1.1 8.2.3 drawing p arameters the mb86290a - compatible interface uses the following parame ters for draw ing : the triangles (right triangle and left triangle) are distinguished according to the locations of three vertices as follows (not used for high - speed 2dtriangle): the following parameters are required for drawing triangles (for h igh - speed 2dtriangle, x and y coordinates of each vertex are specified). note: be careful about the positional relationship between coordinates xs, xus, and xls. for example, in the above diagram, when a right - hand triangle is drawn using the p arameter that shows the coordinates positional relationship xs (upper edge start y coordinate s ) > xus or xs (lower edge start y coordinate s ) > xls, the appropriate picture may not be drawn. v0 upper edge long edge v1 lower edge v2 upper triangle lower triangle v1 v0 v2 upper edge lower edge long edge upper triangle lower triangle right - hand triangle left - hand triangle xus xls ys xs,zs,rs,gs,bs,ss,ts ,qs upper edge start y coordinates dxdy dzdy drdy dgdy dbdy dsdy dtdy dqdy dxudy dxldy lower edge start y coordinates dzdx ,drdx,dgdx,dbdx, dsdx,dtdx,dqdx usn l sn
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 79 specifications rev. 1.1 ys y coordinate s start position of long edge in drawing triangle xs x coordinate s start position of long edge corresponding to ys xus x coordinate s start position of upper edge xls x coordinate s start position of lower edge zs z coordinate s start position of long edge corresponding to ys rs r color value of long e dge corresponding to ys gs g color value of long edge corresponding to ys bs b color value of long edge corresponding to ys ss s coordinate of texture s of long edge corresponding to ys ts t coordinate of texture s of long edge corresponding to ys qs q perspective correction value of texture of long edge corresponding to ys dxdy x dda value of long edge direction dxudy x dda value of upper edge direction dxldy x dda value of lower edge direction dzdy z dda value of long edge direction drdy r dda val ue of long edge direction dgdy g dda value of long edge direction dbdy b dda value of long edge direction dsdy s dda value of long edge direction dtdy t dda value of long edge direction dqdy q dda value of long edge direction usn count of spans of up per triangle lsn count of spans of lower triangle dzdx z dda value of horizontal direction drdx r dda value of horizontal direction dgdx g dda value of horizontal direction dbdx b dda value of horizontal direction dsdx s dda value of horizontal direc tion dtdx t dda value of horizontal direction dqdx q dda value of horizontal direction 8.2.4 anti - aliasing function coral performs anti - aliasing to make jaggies less noticeable and smooth on line edges. to use this function at the edges of primitives, redra w the primitive edges with anti - alias lines. ( the edge of line is blended with a frame buffer color at that time. ideally please draw sequentially from father object.)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 80 specifications rev. 1.1 8.3 bit map processing 8.3.1 blt a rectangular shape in pixel units can be transferred . there a re following types of transfer : 1. transfer from host cpu to drawing frame memory 2. transfer between graphics memories including drawing frame concerning 1 and 2 above, 2 - term logic operation is performed between source and destination data and its result can b e stored. setting a transparent color enables a drawing of a specific pixel with transmission . if part of the source and destination of the blt field are physically overlapped in the display frame, the start address (from which vertex the blt field to be t ransferred) must be set correctly. 8.3.2 pattern data format coral can handle three bit map data formats: indirect color mode (8 bits/pixel), direct color mode (16 bits/pixel), and binary bit map (1 bit/pixel). the binary bit map is used for character/font pat terns, where foreground color is used for bitmap = 1 pixel, and background color (background color can be set to be transparent by setting) is applied for bitmap = 0 pixels.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 81 specifications rev. 1.1 8.4 texture mapping 8.4.1 texture size coral reads texcel corresponding to the specified te xture coordinate s (s, t), and draws that data at the correlated pixel position of the polygon. for the s and t coordinates, the selectable texture data size is any value in the range from 4 to 4096 pixels represented as an exponent of 2. 8.4.2 texture color dra wing of 8 - /16 - bit direct color is supported for the texture pattern. for drawing 8 - bit direct color, only point sampling can be specified for texture interpolation; only de - curl can be specified for the blend mode.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 82 specifications rev. 1.1 8.4.3 texture lapping if a negative or large r than the specified texture pattern size is specified as the texture coordinate s (s, t), according to the setting, one of these options (repeat, cramp or border) is selected for the ?out - of - range? texture mapping. the mapping image for each case is shown below: repeat this just simply masks the upper bits of the applied (s, t) coordinate s . when the texture pattern size is 64 64 pixels, the lower 6 bits of the integer part of (s, t) coordinate s are used for s and t coordinates . cramp when the app lied (s, t) coordinate s is either negative or larger than the specified texture pattern size, cramp the (s, t) coordinate as follows instead of texture : s < 0 s = 0 s > texture x size - 1 s = texture x size - 1 border when the applied (s, t) coordinate is either negative or larger than the specified texture pattern size, the outside of the specified texture pattern is rendered in the ?border? color. repeat cramp border
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 83 specifications rev. 1.1 8.4.4 filtering coral supports two texture filtering modes: point filtering, and bi - linear filtering. point f iltering this mode uses the texture pixel specified by the (s, t) coordinate s as they are for drawing . the nearest pixel in the texture pattern is chosen according to the calculated (s, t) coordinate s . bi - linear filtering the four nearest pix els specified with (s, t) coordinate are blended according to the distance from specified point and used in drawing . 8.4.5 perspective correction this function corrects the distortion of the 3d perspective in the texture mapping. for this correction , the ?q? component of the texture coordinate s (q = 1/w) is set based on the w component of 3d coordinate s of the vertex. when the texture coordinates are large values, the texture may not be drawn correctly when perspective correction is performed. this phenomenon occurs due to the precision limitation of the arithmetical unit for perspective correction. the coordinates for the texture that cannot be drawn normally vary with the value of the q component ; as a guide , when this value, texture coordinate s ( s, t) is smaller than ? 2048 or larger than 2048, normal drawing results are less likely to be obtained. 0.0 0.5 1.0 1.5 2.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 0.5 1.0 1.5 2.0 c 00 c 10 c 01 c 11
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 84 specifications rev. 1.1 8.4.6 texture blending coral supports the following three blend modes for texture mapping: de - curl this mode displays the selected texture pixel color regard less of the polygon color. modulate this mode multiplies the native polygon color (c p ) and selected texture pixel color (c t ) and the result is used for drawing . rendering color is calculated as follows (c o ): c 0 = c t c p stencil this mode select s the disp lay color from the texture color with msb as a flag . msb = 1: texture color msb = 0: polygon color 8.4.7 bi - linear high - speed mode bi - linear filtering is performed at high speed by creating normal texture data in advance with four - pixel redundancy for one pix el. one pixel requires information of about four pixels, so an area of four times the normal area is used. this data format can only be used only for the bi - linear filtering mode; it cannot be used for the point sampling mode. the color mode is limited to 16 - bit color.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 85 specifications rev. 1.1 normal texture layout (8 8 pixels ) texture layout in bi - linear mode (8 8 pixels ) 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 42 43 44 45 46 47 41 49 50 51 52 53 54 55 48 57 58 59 60 61 62 63 56 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 00 01 08 09 01 02 09 10 08 09 16 17 12 13 14 15 16 17 24 25 17 18 25 26 24 25 32 33 25 26 33 34 32 33 40 41 33 34 41 42 40 48 49 41 42 49 50 41 49 56 57 49 50 57 58 48 57 00 01 57 58 01 02 56 0 1 to 6 7 0 1 2 3 4 5 6 7 06 07 14 15 07 00 15 08 09 10 17 18 23 16 15 08 to 30 31 22 23 31 24 23 16 to 38 39 30 31 39 32 31 24 to 54 55 46 47 to 38 39 46 47 39 32 47 40 55 48 47 40 to 62 63 54 55 63 56 55 48 to 06 07 62 63 07 00 63 56 to
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 86 specifications rev. 1.1 8.5 rendering 8.5.1 tiling tiling reads the pixel color from the correlated tiling pattern and maps it onto the polygon. the tiling determi nes the pixel on the pattern read by pixel coordinate s to be drawn, irrespective of position and size of primitive . t he tiling pattern size is limited to within 64 64 pixels. (at 16 - bit color ) example of tiling 8.5.2 alpha blending alpha blending blend s the drawn in frame buffer to - be - drawn pixel or pixel already according to the alpha value set in the alpha register. this function cannot be used simultaneously with logic operation drawing . it can be used only when the direct color mode (16 bits/pixel ) is used. the blended color c is calculated as shown below when the color of the pixel to be drawn is c p , the color of frame buffer is c f , and the alpha value is a: c = c p a + (1 - a) c f the alpha value is specified as 8 - bit data. 00h means alpha value 0% and ffh means alpha value 100%. when the texture mapping function is enabled, the following blending modes can be selected : normal blends post texture mapping color with frame buffer color stencil uses msb of texcel color for on/off control : msb = 1: texcel color msb = 0: frame buffer color stencil alpha uses msb of texcel color for a /off control : msb = 1: alpha blend texcel color and current frame buffer color msb = 0: frame buffer color note: msb of frame buffer is drawn msb of texcel in both s tencil and stencil alpha mode. therefore in case msb of texcel is msb=0, a color of frame buffer is frame buffer, but msb of frame buffer is set to 0.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 87 specifications rev. 1.1 8.5.3 logic operation this mode executes a logic operation between the pixel to be drawn and the one already d rawn in frame buffer and its result is drawn . alpha blending cannot be used when this function is specified . type id operation type id operation clear 0000 0 and 0001 s & d copy 0011 s or 0111 s | d nop 0101 d nand 1110 ! (s & d) set 1111 1 nor 1000 ! (s | d) copy inverted 1100 !s xor 0110 s xor d invert 1010 !d equiv 1001 ! (s xor d) and reverse 0010 s & !d and inverted 0100 !s & d or reverse 1011 s | !d or inverted 1101 !s | d 8.5.4 hidden plane management coral supports the z buffer for hidden plane management. this function compares the z value of a new pixel to be drawn and the existing z value in the z buffer. display/not display is switched according to the z - compare mode setting. define the z - buffer access options in the zwritemask mode. the z compare operation type is determined by the z compare mode. either 16 or 8 bits can be selected f or the z - value. 1 compare z values, no z value write overwrite zwritemask 0 compare z values , z value write z compare mode code condition never 000 neve r draw always 001 always draw less 010 draw if pixel z value < current z buffer value lequal 011 draw if pixel z value current z buffer value equal 100 draw if pixel z value = current z buffer value gequal 101 draw if pixel z value 3 current z buffe r value greater 110 draw if pixel z value > current z buffer value notequal 111 draw if pixel z value ! = current z buffer value
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 88 specifications rev. 1.1 8.6 drawing attributes 8.6.1 line draw ing attributes in drawing line s , the following attributes apply: line draw ing attributes drawi ng attribute description line width line width selectable in range of 1 to 32 pixels broken line specify broken line pattern in 32 - bit data anti - alias line edge smoothed when anti - aliasing enabled 8.6.2 triangle draw ing attributes in drawing triangle s, the f ollowing attributes apply (these attributes are disabled in high - speed 2dtriangle) . texture mapping and tiling have separated texture attributes: triangle draw ing attributes drawing attribute description shading gouraud shading or flat shading selectable . in case of indirect color mode, gray scale gouraud shading is possible. alpha blending set alpha blend ing enable /disable per polygon alpha blending coefficient set color blend ing ratio of alpha blend ing how to set gray scale gouraud shading 1. set frust um bit of gmdr0 register to 0. 2. set identity matrix. 3. set mdr2 register to the below. sm bit = 1, zc bit = 0, zw bit = 0, bm bit = 00, tt bit = 00 4. set gg bit of mdr7 register to 1. 5. execute drawing by same method as a direct color gouraud shading object. note : - please don ? t use g_begine command. - please don ? t use floating data format in g_vertex command. - r (red) parameter is used as a color parameter. 6. set gg bit of mdr7 register to 0 after rendering.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 89 specifications rev. 1.1 8.6.3 texture attributes in texture mapping , t he following attributes apply: texture attributes drawing attribute description texture mode select either texture mapping or tiling texture memory mode select either internal texture buffer or external graphics memory to use in texture mapping texture filter select either point sampling or bi - linear filtering texture coordinate s correction select either linear or perspective correction texture wrap select either repeat or cramp of texture pattern texture blend mode select either decal or modulate bi - linear high - speed mode texture data is created in a dedicated format to perform high - speed bi - linear filtering.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 90 specifications rev. 1.1 8.6.4 blt attributes in blt draw ing , the following attributes apply: blt attributes drawing attribute description logic operation mode specify tw o source logic operation mode transparency mode set transparent copy mode and transparent color alpha map mode blend a color according to alpha map 8.6.5 character pattern drawing attributes character pattern drawing drawing attribute description character pattern enlarge/shrink 2 2, 2 horizontal, 1/2 1/2, 1/2 horizontal character pattern color set character color and background color transparency/non - transparency set background color to transparency/non - transparency
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 91 specifications rev. 1.1 8.7 bold line 8.7.1 starting and endin g points in the cremson bold line mode, the starting and ending point s are vertical to the principal axis. in the coral bold line mode, the starting and ending point s are vertical to the theoretical line. caution: coral bold line is generated by different algorithm. thus drawing position is little bit different from other primitive. cremson bold line mode coral bold line mode
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 92 specifications rev. 1.1 8.7.2 broken line pattern the broken line pattern vertical to the theoretical line (the coral broken line pattern) is supported. in the cremson bold line mode, lines c an be drawn using the broken line pattern vertical to the cremson - compatible principal axis (the cremson broken line pattern), and can also be drawn using the coral broken line pattern. in the coral bold line mode, only the coral broken line pattern is sup ported. interpolation of broken line pattern two types of interpolation modes are supported: no interpolation mode: interpolation is not performed. broken line pattern reference address fix mode: the same broken line pattern is referenced fo r several pixels before and after the joint of the bold line. any pixel count can be set by the user. coral bold and broken lines (1) (2) broken line pattern made vertical starting point made vertical; ending point made vertical edging not performed interpolation of bold line joint not performed interpolation of broken line pattern reference performed (1) (2) (1) (2) edging not performed interpolation of bold line jo int not performed broken line pattern reference address fixed
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 93 specifications rev. 1.1 8.7.3 edging the edging line is supported. the line body and edging section can have depth information (z offset). this mechanics makes it possi ble to easily represent a good connection of the overlaid part of the edging line. for example, when the line body depth information and edging section depth information are the same, the drawing result of the edging line is like the intersection shown in the figure below. also, when the line body depth information and edging section depth information are different, the drawing result of the edging line is like the solid intersection shown in the figure below. edging intersection solid intersection control by depth information
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 94 specifications rev. 1.1 8.7.4 interpolation of bold line jo int in the bold line joint interpolation mode, the bold line joint is interpolated using a triangle as shown in the figure below. the edging line joint is also interpolated using a triangle, but the said depth information makes it possible to represent a g ood connection as shown in the figure below. caution: sometime joint shape looks not perfect. ( using approximate calculation) interpolation of bold line joint interpolation using triangle edging interpolation can also be performed.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 95 specifications rev. 1.1 9 display list 9.1 overview display list is a set of display list commands, parameters and pattern data. all display list commands stored in a display list are executed consequently . the display list is transferred to the display list fifo by one of the following methods: write to display fifo by cpu transfer from main memory to display fifo by external dma transfer from grap hics memory to display fifo by register set ting display list command - 1 data 1 - 1 data 1 - 2 data 1 - 3 display list command - 2 data 2 - 1 data 2 - 2 data 2 - 3 display list
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 96 specifications rev. 1.1 9.1.1 header format the format of the display list header is shown below. format list format 31 24 23 16 15 0 format 1 type reserved reserved format 2 type count address format 3 type reserved reserved vertex format 4 type reserved reserved flag vertex format 5 type command reserved format 6 type command coun t format 7 type command reserved vertex format 8 type command reserved flag vertex format 9 type reserved reserved flag format 10 type reserved count type reserved reserved format 11 count description of each field type display list type command command count count of data excluding header address address value used at data transfer vertex vertex number flag attribute flag peculiar to display list command vertex number specified in vertex code vertex vertex number (line) vertex number (trian gle) 00 v0 v0 01 v1 v1 10 setting prohibited v2 11 setting prohibited setting prohibited 9.1.2 parameter format the parameter format of the geometry command depends on the value set in the d field of gmdr0. when the d field is ?00?, all parameters are hand led in the floating - point format. when the d field is ?01?, colors are handled as the packed rgb format, and others are handled as the fixed - point format. when the d field is ?11?, xy is handled as the packed integer format, colors are handled as the pac ked rgb format, and others are handled as the fixed - point format. in the following text, the floating - point format is suffixed by .float , the fixed point format is suffixed by .fixed , and the integer format is suffixed by .int . set gmdr0 properly to match parameter suffixes. rendering command parameters conform to the mb86290a data format.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 97 specifications rev. 1.1 9.2 geometry commands 9.2.1 geometry command list coral geometry commands and each command code are shown in the table below. type command description g_nop ? no operation g_b egin see geometry command code table . specifies primitive type and pre - processes g_begincont ? specifies primitive type (vertex processing in same mode as previous mode) g_begin e see geometry command code table . specifies primitive type and pre - processes this command is used at execution of the coral extended function. g_begin e cont ? specifies primitive type (vertex processing in same mode as previous mode) this command is used at execution of the coral extended function. g_end ? ends primitive this com mand is used at execution of g_begin or g_begincont g_end e ? ends primitive this command is used at execution of g_begine or g_beginecont. g_vertex ? sets vertex parameter and draws g_vertex log ? sets vertex parameter and draws outputs device coordinate s g_vertex noplog ? only outputs device coordinates g_init ? initialize geometry engine g_viewport ? scale to screen coordinates (x, y) and set origin offset g_depthrange ? scale to screen coordinate s (z) and set origin offset g_loadmatirix ? load geom etri c transformation matrix g_viewvolumexyclip ? set boundary value (x, y) of view volume clip g_viewvolumezclip ? set boundary value (z) of view volume clip g_viewvolumewclip ? set boundary value (w) of view volume clip overlapxyofft see command table . sets xy offset at shading overlapzofft see command table . sets z offset of shade primitive; sets z offset of edge primitive; sets z offset of interpolation primitive at 2d drawing with top - left non - applicable dc_logoutaddr ? sets starting address of de vice coordinates output setmoderegister see command table . sets drawing extended mode register setgmoderegister see command table . sets geometry extended mode register setcolorregister see command table . sets body color, shade color, and edge color set lvertex2i ? pass through high - speed 2dline drawing register setlvertex2ip ? pass through high - speed 2dline drawing register
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 98 specifications rev. 1.1 type code table type code g_nop 0010_0000 g_begin 0010_0001 g_begincont 0010_0010 g_end 0010_0011 g_vertex 0011_0000 g_vert ex log 0011_0010 g_vertex noplog 0011_0011 g_init 0100_0000 g_viewport 0100_0001 g_depthrange 0100_0010 g_loadmatirix 0100_0011 g_viewvolumexyclip 0100_0100 g_viewvolumezclip 0100_0101 g_viewvolumewclip 0100_0110 setlvertex2i 0111_0010 setlvertex2i p 0111_0011 setmoderegister 1100_0000 setgmoderegister 1100_0001 overlapxy0fft 1100_1000 overlapz0fft 1100_1001 dc _ logoutaddr 1100_1100 setcolorregister 1100_1110 g_begin e 11 1 0_0001 g_begin conte 11 1 0_0010 g_ende 11 1 0_0011
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 99 specifications rev. 1.1 geometry command code table ( 1 ) integer setup type in setup processing, ?xy? is calculated in the integer format and other parameters are calculated in the floating - point format. command code points.int 0001_0000 lines.int 0001_0001 polygon.int 0001_0010 triangles.int 0001 _0011 line_strip.int 0001_0101 triangle_strip.int 0001_0111 triangle_fan.int 0001_1000 ( 2 ) ?unclipped? integer setup type this command does not clip the view volume. only ?xy? is enabled as the input parameter. in setup processing, ?xy? is calculated i n the integer format. the screen projection (gmdr0[0]=1) performed using this command is not assured. command code nclip_points.int 0011_0000 nclip_lines.int 0011_0001 nclip_polygon.int 0011_0010 nclip_triangles.int 0011_0011 nclip_line_strip.int 001 1_0101 nclip_triangle_strip.int 0011_0111 nclip_triangle_fan.int 0011_1000
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 100 specifications rev. 1.1 9.2.2 explanation of geometry commands g_nop (format 1) 31 24 23 16 15 0 g_nop reserved reserved no operation g_init (format 1) 31 24 23 16 15 0 g_init reserved reserved the g _ init command initializes geometry engine. execute this command before processing. g_end (format 1) 31 24 23 16 15 0 g_end reserved reserved the g_end command ends one primiti ve. the g_vertex command must be specified between the g_begin or g_begincont command and g_end command.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 101 specifications rev. 1.1 g_begin (format 5) 31 24 23 16 15 0 g_begin command reserved the g_begin command sets types of primitive for geometry pr ocessing and drawing. a vertex is set and drawn by the g_vertex command. the g_vertex command must be specified between the g_begin or g_begincont command and g_end command. command: points* handles primitive as point lines* handles primitive as indepen dent line polygon* handles primitive as polygon triangles* handles primitive as independent triangle line_strip* handles primitive as line strip triangle_strip* handles primitive as triangle strip triangle_fan* handles primitive as triangle fan usable com binations of gmdr0 mode setting and primitives are as follows: unclipped primitives (nclip*) (st,z,c) point line triangle polygon (0,0,0) ? ? ? ? other than above primitives other than unclipped primitives (st,z,c) point line triangle polygon (* 2) (0,0,0) ? ? ? ? (0,0,1) ? (0,1,0) (*3) ? ? ? (0,1,1) ? (1,x,x) ? ? (*1) *1: shading is not assured. *2: in case of drawing polygon with z,st=1, the algorithm is approximate calculation. the triangle algorithm is more accurate. * 3: please use a geometry lines which coordinates set to same value. and set gmdr1/gmdr1e to "end point drawn" and set mdr1 to "z compare enable", "solid", "1 pixel line width". g_begincont (format 1) 31 24 23 16 15 0 g_begincon t reserved reserved when the primitive type set by the g_begin command the last time and drawing mode are not changed , the g_begincont command is used instead of the g_begin command. the g_begincont command is processed faster than the g_begin command. t he packet that can be set between the g_end packet set just before and the g_begincont packet is only ?foreground color setting by the setregister packet.? the g_vertex command must be specified between the g_begin or g_begincont command and g_end command . no primitive type need be specified in the g_begincont command.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 102 specifications rev. 1.1 g_begin e (format 5) 31 24 23 16 15 0 g_begin command reserved this is the extended g_begin command. when using the following functions, this command must be exe cuted instead of g_begin . mode register mdr1s/mdr1b/mdr1tl/mdr2s/mdr2tl/gmdr1e/gmdr2e log output of device coordinates g_vertexlog/g_vertexnoplog the g_begine command sets types of primitive for geometry processing and drawing. vertex setting/drawing usi ng the above extended function is performed using the g_vertex* command. the g_vertex* command must be set between the g_begine command (or the g_beginecont command) and the g_ende command. command: points* handles primitive as point lines* handles primi tive as independent line interpolation of the joint and broken line pattern is not supported. polygon* handles primitive as polygon triangles* handles primitive as independent triangle line_strip* handles primitive as line strip triangle_strip* handles pr imitive as triangle strip triangle_fan* handles primitive as triangle fan usable combinations of gmdr0 mode setting and primitives are as follows: unclipped primitives (nclip*) (st,z,c) point line triangle polygon (0,0,0) ? ? ? ? other than above primitives other than unclipped primitives (st,z,c) point line triangle polygon (0,0,0) ? ? ? ? (0,0,1) ? (0,1,0) ? ? ? ? (0,1,1) ? (1,x,x) ? ? (*1) *1: shading is not assured.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 103 specifications rev. 1.1 g_begin e cont (format 1) 31 24 23 16 15 0 g_begincont reserved reserved when the primitive type set by the g_begin e command the last time and drawing mode are not changed , the g_begin e cont command is used instead of the g_begin e command. the g_begin e cont command is processed fas ter than the g_begin e command. the packet that can be set between the g_end packet set just before and the g_begincont packet is only ?foreground color setting by the setregister packet.? the g_vertex command must be specified between the g_begin or g_beg incont command and g_end command. no primitive type need be specified in the g_begincont command.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 104 specifications rev. 1.1 g_vertex / g_vertex log/ g_vertex noplog (format 1) when data format is floating - point format 31 24 23 16 15 0 g_vertex reserved rese rved x.float y.float z.float r.float g.float b.float s.float t.float when data format is fixed - point format 31 24 23 16 15 0 g_vertex reserved reserved x.fixed y.fixed z.fixed r.int g.int b.int s.fixed t.fixed when data format is packed integer format 31 24 23 16 15 0 g_vertex reserved reserved y.int x.int z.fixed r.ing g.int b.int s.fixed t.fixed the g_vertex command sets vertex parameters and processes and draws the geometry o f the primitive specified by the g_begin * command. note the following when using this command: required parameters depend on the setting of the gmdr0 register. proper values must be set as the mode values of the mdr0 to mdr4 registers to be finally refle cted at drawing. that is, when ?z? comparison is made (zc bit of mdr1 or mdr2 = 1), the z bit of the gmdr0 register must be set to 1. when gouraud shading is performed (sm bit of mdr2 = 1), the c bit of the gmdr0 register must be set to 1. when texture mapping is performed (tt bits of mdr2 = 10), the st bit of the gmdr0 register must be set to 1. when the z bit of the gmdr0 register is 0, input ?z? (zoc) is treated as ?0?. use values normalized to 0 and 1 as texture coordinates (s, t). when the color rgb is floating - point format, use values normalized to 0 and 1 as the 8 - bit color value. for the packed rgb, use the 8 - bit color value directly. the gmdr1 register is valid only for line drawing; it is ignored in primitives other than line. the gmdr2 registe r matters only when a triangle ( excluding a polygon) is drawn. at primitives other than triangle, set ?0?. the use of both g_begine(g_beginecont) to g_ende, and g_vertexlog/noplog is not assured. g_vertexnoplog, except for the primitive as point is not as sured.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 105 specifications rev. 1.1 a vertex data is processed at every time. for example, the coral draws interpolation of bold line joint, edging line, shadows at every vertices. g_viewport (format 1) 31 24 23 16 15 0 g_viewport reserved reserved x_scali ng.float/fixed x_offset.float/fixed y_scaling.float/fixed y_offset.float/fixed the g_viewport command sets the ?x,y? scale/offset value used when normalized device coordinate s (ndc) is transformed into device coordinate s (dc). g_depthrange (format 1) 31 24 23 16 15 0 g_depthrange reserved reserved z_scaling.float/fixed z_offset.float/fixed the g_depthrange command sets the ?z? scale/offset value used when an ndc is transformed into a dc. g_loadmatrix (format 1) 31 2 4 23 16 15 0 g_loadmatrix reserved reserved matrix_a0.float/fixed matrix_a1.float/fixed matrix_a2.float/fixed matrix_a3.float/fixed matrix_b0.float/fixed matrix_b1.float/fixed matrix_b2.float/fixed matrix_b3.float/fixed matrix _c0.float/fixed matrix_c1.float/fixed matrix_c2.float/fixed matrix_c3.float/fixed matrix_d0.float/fixed matrix_d1.float/fixed matrix_d2.float/fixed matrix_d3.float/fixed the g_loadmatrix command sets the transformation matrix used when object coord inate s (oc) is transformed into clip coordinate s (cc).
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 106 specifications rev. 1.1 g_viewvolumexyclip (format 1) 31 24 23 16 15 0 g_viewvolumexyclip reserved reserved xmin.float/fixed xmax.float/fixed ymin.float/fixed ymax.float/fixed the g_viewvolume xyclip command sets the x,y coordinates of the clip boundary value in view volume clipping. g_viewvolumezclip (format 1) 31 24 23 16 15 0 g_viewvolumezclip reserved reserved zmin.float/fixed zmax.float/fixed the g_viewvolumez clip command sets the z coordinate s of the clip boundary value in view volume clipping. g_viewvolumewclip (format 1) 31 24 23 16 15 0 g_viewvolumewclip reserved reserved wmin.float/fixed the g_viewvolumewclip command sets the w coordinate s of the clip boundary value in view volume clipping (minimum value only).
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 107 specifications rev. 1.1 overlapxyofft (format5) 31 24 23 16 15 0 overlapxyofft command reserved y offset x offset the overlapxyofft command sets the xy offset of t he shade primitive relative to the body primitive at shading drawing . shadow shape is same as body. command: command code explanation shadowxy 0000_0000 shadowxy command sets the xy offset of the shade primitive relative to the body primitive. shadowxy compsition 0000_0001 shadowxycomposition command sets the xy offset of the shade synthetic primitive relative to the body primitive. it command synthesizes a shade from the relationship between the xy offset set using shadowxy and this xy offset. this com mand is enabled for only lines. overlapzofft (format5) 31 24 23 16 15 0 overlapzofft command reserved don?t care z offset note: when mdr0 zp = 1, only lower 8 bits are enabled. 31 24 23 16 15 0 ov erlapzofft packed_onbs reserved s _ z offset b _ z offset n _ z offset o _ z offset the overlapzofft command sets the z offset of the shade primitive relative to the body primitive, sets the z - offset of the edge primitive relative to the body primitive, and sets the z offset of the interpolation primitive relative to the body primitive, with the top - left rule non - applicable in effect. at this time, the following relationship must be satisfied when, for example, greater is specified for the z value comparison mode : body primitive > top - left rule non - applicable interpolation primitive > edge primitive > shade primitive command: command code explanation origin 0000_0000 origin command sets the z offset of the body primitive. when drawing one primitive below the o ther primitive (for example, when drawing a solid intersection), this z offset is changed. when drawing an ordinary intersection, set the same z offset as other primitives. nontopleft 0000_0001 nontopleft command sets the z offset of the interpolation pr imitive, with the top - left non - applicable. border 0000_0010 border command sets the z offset of the edge primitive. shadow 0000_0011 shadow command sets the z offset of the shade primitive. packed_onbs 0000_0111 packed_onbs command sets the above four t ypes of z offsets.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 108 specifications rev. 1.1 dc_logoutaddr (format5) 31 24 23 16 15 0 overlapxyofft command reserved 000000 logoutaddr the dc_logoutaddr command sets the starting address of the log output destination of the device coordinates. setmod eregister (format5) 31 24 23 16 15 0 setmoderegister command reserved mdr1*/mdr2* the setmoderegister command sets the mode register for shade primitive, for edge primitive, and for top - left non - applicable primitive. at drawin g of these primitives, also set the mode register (mdr1/mdr2) for the body primitive, using this packet. command: command code explanation mdr1 0000_0000 mdr1 command sets mdr1 for the body primitive. mdr1s 0000_0010 mdr1s command sets mdr1 for the shad e primitive. mdr1b 0000_0100 mdr1b command sets mdr1 for the edge primitive. mdr2 0000_0001 mdr2 command sets mdr2 for the body primitive. mdr2s 0000_0011 mdr2s command sets mdr2 for the shade primitive. mdr2lt 0000_0111 mdr2lt command sets mdr2 for th e top - left non - applicable primitive. setgmoderegister (format5) 31 24 23 16 15 0 set g moderegister command reserved gmdr1e/gmdr2e the setgmoderegister command sets the geometry extended mode register. command: command code ex planation gmdr1e 0001_0000 gmdr1e command sets gmdr1e and at the same time, updates gmdr1. gmdr2e 0010_0000 gmdr2e command sets gmdr2e and at the same time, updates gmdr2.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 109 specifications rev. 1.1 setcolorregister (format5) 31 24 23 16 15 0 setcolor register command reserved fgc8/16/24 the setcolorregister command sets the foreground color and background color of the body primitive, shade primitive, and edge primitive. command s : command code explanation forecolor 0000_0000 forecolor command sets t he foreground color for the body primitive. backcolor 0000_0001 backcolor command sets the background color for the body primitive. forecolor shadow 0000_0010 forecolor shadow command sets the foreground color for the shade primitive. backcolor shadow 0000 _0011 backcolor shadow command sets the background color for the shade primitive. forecolor border 0000_0100 forecolor border command sets the foreground color for the edge primitive. backcolor border 0000_0101 backcolor border command sets the background col or for the edge primitive. setregister (format 2) 31 24 23 16 15 0 setregister count address (val 0) (val 1) ? (val n) the setregister command is upper compatible with cremson setregister . it can specify the address of a register in the geometry engine. setlvertex2i (format 1) 31 24 23 16 15 0 setlvertex2i reserved reserved lx0dc ly0dc the setlvertex2i command issues the setregister_lxodc/lyodc command (mb86290a command to set starting vertex at line drawing) in the geometry fifo interface. this performs processing faster than when the setregister_lxodc/lyodc command is input directly to the geometry fifo. setlvertex2ip (format 1) 31 24 23 16 15 0 setlvertex2ip res erved reserved ly0dc lx0dc the setlvertex2ip command supports packed xy of setlvertex21.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 110 specifications rev. 1.1 9.3 rendering command 9.3.1 command list the following table lists coral rendering commands and their command codes. type command description nop ? no operation interrupt ? interrupt request to host cpu sync ? synchronization with events setregister ? set s data to register normal set s data to high - speed 2dtriangle vertex register setvertex2i polygonbegin initializes border rectangle calculation of multiple vertices ran dom shape polygonend clear s polygon flag after drawing pol y gon draw flush_fb/z flushes drawing pipelines drawpixel pixel draws point drawpixelz pixelz draws point with z xvector draw s line ( principal axis x) yvector draw s line ( principal a xis y) antixvector draw s line with anti - alias option ( principal axis x) drawline antiyvector draw s line with anti - alias option ( principal axis y) zerovector draw s high - speed 2dline ( with vertex 0 as starting point ) drawline2i drawline2ip onevector draw s high - speed 2dline ( with vertex 1 as starting point ) trapright draw s right triangle drawtrap trapleft draw s left triangle trianglefan draw s high - speed 2dtriangle drawvertex2i drawvertex2ip flagtrianglefan draw s high - speed 2dtriangle for multiple vertices random shape bltfill draws rectangle with single color drawrectp clearpolyflag clear s polygon flag buffer bltdraw draw s blt (16 - bit) drawbitmapp bitmap draw s binary bit map (character) drawbitmaplargep bltdraw draws blt (32 - bit) topleft blt transfer from top left coordinates topright blt transfer from top right coordinates bottomleft blt transfer from bottom left coordinates bltcopyp bltcopy - alternatep bottomright blt transfer from bottom right coordinates loadtexture load s tex ture pattern loadtexturep loadtile load s tile pattern loadtexture load s texture pattern from local memory blttexturep loadtile load s tile pattern from local memory
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 111 specifications rev. 1.1 bltcopyalt - alphablendp ? alpha blending is supported (see the alpha map). bltcopyalternatep
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 112 specifications rev. 1.1 type code table type code drawpixel 0000_0000 drawpixelz 0000_0001 drawline 0000_0010 drawline2i 0000_0011 drawline2ip 0000_0100 drawtrap 0000_0101 drawvertex2i 0000_0110 drawvertex2ip 0000_0111 drawrectp 0000_1001 drawbitmapp 0000_1011 bitcopyp 000 0_1101 bitcopyalternatep 0000_1111 loadtexturep 0001_0001 blttexturep 0001_0011 bltcopyalt alphablend p 0001 _1111 setvertex2i 0111_0000 setvertex2ip 0111_0001 draw 1111_0000 setregister 1111_0001 sync 1111_1100 interrupt 1111_1101 nop 1111_1111
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 113 specifications rev. 1.1 command code table (1) command code pixel 000_00000 pixelz 000_00001 xvector 001_00000 yvector 001_00001 xvectornoend 001_00010 yvectornoend 001_00011 xvectorblpclear 001_00100 yvectorblpclear 001_00101 xvectornoendblpclear 001_00110 yvectornoen dblpclear 001_00111 antixvector 001_01000 antiyvector 001_01001 antixvectornoend 001_01010 antiyvectornoend 001_01011 antixvectorblpclear 001_01100 antiyvectorblpclear 001_01101 antixvectornoendblpclear 001_01110 antiyvectornoendblpclear 001_01111 zerovector 001_10000 onevector 001_10001 zerovectornoend 001_10010 onevectornoend 001_10011 zerovectorblpclear 001_10100 onevectorblpclear 001_10101 zerovectornoendblpclear 001_10110 onevectornoendblpclear 001_10111 antizerovector 001_11000 antio nevector 001_11001 antizerovectornoend 001_11010 antionevectornoend 001_11011 antizerovectorblpclear 001_11100 antionevectorblpclear 001_11101 antizerovectornoendblpclear 001_11110 antionevectornoendblpclear 001_11111
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 114 specifications rev. 1.1 command code table (2) comman d code bltfill 010_00001 bltdraw 010_00010 bitmap 010_00011 topleft 010_00100 topright 010_00101 bottomleft 010_00110 bottomright 010_00111 loadtexture 010_01000 loadtile 010_01001 trapright 011_00000 trapleft 011_00001 trianglefan 011_00010 f lagtrianglefan 011_00011 flush_fb 110_00001 flush_z 110_00010 polygonbegin 111_00000 polygonend 111_00001 clearpolyflag 111_00010 normal 111_11111
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 115 specifications rev. 1.1 9.3.2 details of rendering commands all parameters belonging to their command are stored in relevant regist ers. the definition of each parameter is explained in the section of each command. nop (format1) 31 24 23 16 15 0 nop reserved reserved no operation interrupt (format1) 31 24 23 16 15 0 interrupt res erved reserved the interrupt command generates interrupt request to host cpu . sync (format9) 31 24 23 16 15 4 0 sleep reserved reserved flag the sync command suspends all subsequent display list processing until event set in fl ag detected . flag: bit number 4 3 2 1 0 bit field name reserved reserved reserved reserved vblank bit 0 vblank vblank synchronization 0 no operation 1 wait for vsync detection
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 116 specifications rev. 1.1 setregister (format2) 31 24 23 16 15 0 se tregister count address (val 0) (val 1) (val n) the setregister command sets data to sequential registers . count: data word count (in double - word unit) address: register address set the value of the address for setregister given in the register list. when transferring two or more data, set the starting register address. setvertex2i (format8) 31 24 23 16 15 4 3 2 1 0 setvertex2i command reserved flag vertex xdc ydc the setvertex2i command sets vertices data for high - sp eed 2dline or high - speed 2dtriangle to registers . commands: normal set s vertex data (x, y). polygonbegin start s calculation of circumscribed rectangle for random shape to be drawn. calculate vertices of rectangle including all vertices of random shape d efined between polygonbegin and polygonend . flag: not used setvertex2ip (format8) 31 24 23 16 15 4 3 2 1 0 setvertex2i command reserved flag vertex ydc xdc the setvertex2ip command sets vertices data for high - speed 2dline or high - speed 2dtriangle to registers . only the integer (packed format) can be used to specify these vertices. command s : normal set s vertices data. polygonbegin start s calculation of circumscribed rectangle of random shape to be drawn. calculate vertices of re ctangle including all vertices of random shape defined between polygonbegin and polygonend . flag: not used
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 117 specifications rev. 1.1 draw (format5) 31 24 23 16 15 0 draw command reserved the draw command executes draw ing command . all parameters requir ed for draw ing command execution must be set at their appropriate registers. commands: polygonend draw s polygon end . fill s random shape with color according to flags generated by flagtrianglefan command and information of circumscribed rectangle generated by polygonbegin command. flush_fb flushes drawing data in the drawing pipeline into the graphics memory. place this command at the end of the display list. flush_z flushes z value data in the drawing pipeline into the graphics memory. when using the z buffer, place this command together with the flush_fb command at the end of the display list. drawpixel (format5) 31 24 23 16 15 0 deawpixel command reserved pxs pys the drawpixel command draws pixel . command: pixel draw s pixel without z value. drawpixelz (format5) 31 24 23 16 15 0 deawpixel command reserved pxs pys pzs the drawpixelz command draws pixel with z value. command: pixelz draws pixel with z value.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 118 specifications rev. 1.1 drawline (format5) 31 24 23 16 15 0 drawline command reserved lpn lxs lxde lys lyde the drawline command draws line . it start s drawing after setting all parameters at line draw registers. commands: xvector draw s line (principal axis x). yvector draw s line (principal axis y). xvectornoend draw s line (principal axis x, and without end point drawing ). yvectornoend draw s line (principal axis y , and without end point drawing ). xvectorblpclear draw s line (principal axis x, and prior to drawing, brok en line pattern reference position cleared) . yvectorblpclear draw s line (principal axis y, and prior to drawing, broken line pattern reference position cleared) . xvectornoendblpclear draw s line (principal axis x, without end point drawing and prior to dr awing, broken line pattern reference position cleared) . yvectornoendblpclear draw s line (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antixvector draw s anti - alias line (principal axis x). antiyvector draw s anti - alias line (principal axis y). antixvectornoend draw s anti - alias line (principal axis x, and without end point drawing ). antiyvectornoend draw s anti - alias line (principal axis y , and without end point drawing ). antixvectorblp clear draw s anti - alias line (principal axis x and prior to drawing, broken line pattern reference position cleared) . antiyvectorblpclear draw s anti - alias line (principal axis y and prior to drawing, broken line pattern reference position cleared) . antixv ectornoendblpclear draw s anti - alias line (principal axis x, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antiyvectornoendblpclear draw s anti - alias line (principal axis y, without end point drawing and pr ior to drawing, broken line pattern reference position cleared) .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 119 specifications rev. 1.1 drawline2i (format7) 31 24 23 16 15 0 drawline2i command reserved vertex lfxs 0 lfys 0 the drawline2i command draws high - speed 2d l ine . it start s drawing afte r setting parameters at the high - speed 2dline draw ing registers. integer data can only be used for coordinates . commands: zerovector draw s line from vertex 0 to vertex 1. onevector draw s line from vertex 1 to vertex 0. zerovectornoend draw s line from ve rtex 0 to vertex 1 ( without drawing end point ) . onevectornoend draw s line from vertex 1 to vertex 0 ( without drawing end point ) . zerovectorblpclear draw s line from vertex 0 to vertex 1 (principal axis x, and prior to drawing, broken line pattern referenc e position cleared) . onevectorblpclear draw s line from vertex 1 to vertex 0 (principal axis y, and prior to drawing, broken line pattern reference position cleared) . zerovectornoendblpclear draw s line from vertex 0 to vertex 1 (principal axis x, without end point drawing and prior to drawing, broken line pattern reference position cleared) . onevectornoendblpclear draw s line from vertex 1 to vertex 0 (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antizerovector draw s anti - alias line from vertex 0 to vertex 1. antionevector draw s anti - alias line from vertex 1 to vertex 0. antizerovectornoend draw s anti - alias line from vertex 0 to vertex 1 ( without end point ) . antionevectornoend draw s a nti - alias line from vertex 1 to vertex 0 ( without end point ) . antizerovectorblpclear draw s anti - alias line from vertex 0 to vertex 1 (principal axis x and prior to drawing, broken line pattern reference position cleared) . antionevectorblpclear draw s anti - alias line from vertex 1 to vertex 0 (principal axis y and prior to drawing, broken line pattern reference position cleared) . antizerovectornoendblpclear draw s anti - alias line from vertex 0 to vertex 1 (principal axis x, without end point drawing and pri or to drawing, broken line pattern reference position cleared) . antionevectornoendblpclear draw s anti - alias line from vertex 1 to vertex 0 (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 120 specifications rev. 1.1 drawline2ip (format7) 31 24 23 16 15 0 drawline2ip command reserved vertex lfys lfxs the drawline2ip command draws high - speed 2d l ine . it start s drawing after setting parameters at high - speed 2dl i ne draw ing registers. only packed integer data can be used for coordinates . commands: zerovector draw s line from vertex 0 to vertex 1. onevector draw s line from vertex 1 to vertex 0. zerovectornoend draw s line from vertex 0 to vertex 1 ( without drawing end point ) . onevectornoend draw s line from vertex 1 to vertex 0 ( without drawing end point ) . zerovectorblpclear draw s line from vertex 0 to vertex 1 (principal axis x, and prior to drawing, broken line pattern reference position cleared) . onevectorblpclear draw s line from vertex 1 to vertex 0 (principal axis y, and prior to drawing, broken line pattern reference position cleared) . zerovectornoendblpclear draw s line from vertex 0 to vertex 1 (principal axis x, without end point drawing and prior to drawing, broken line pattern refe rence position cleared) . onevectornoendblpclear draw s line from vertex 1 to vertex 0 (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antizerovector draw s anti - alias line from vertex 0 to vertex 1. antionevector draw s anti - alias line from vertex 1 to vertex 0. antizerovectornoend draw s anti - alias line from vertex 0 to vertex 1 ( without end point ) . antionevectornoend draw s anti - alias line from vertex 1 to vertex 0 ( without end point ) . a ntizerovectorblpclear draw s anti - alias line from vertex 0 to vertex 1 (principal axis x and prior to drawing, broken line pattern reference position cleared) . antionevectorblpclear draw s anti - alias line from vertex 1 to vertex 0 (principal axis y and prio r to drawing, broken line pattern reference position cleared) . antizerovectornoendblpclear draw s anti - alias line from vertex 0 to vertex 1 (principal axis x, without end point drawing and prior to drawing, broken line pattern reference position cleared) . antionevectornoendblpclear draw s anti - alias line from vertex 1 to vertex 0 (principal axis y, without end point drawing and prior to drawing, broken line pattern reference position cleared) .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 121 specifications rev. 1.1 drawtrap (format5) 31 24 23 16 15 0 drawtrap command reserved ys 0 xs dxdy xus dxudy xls dxldy usn 0 lsn 0 the drawtrap command draws triangle . it start s drawing after setting parameters at the triangle draw ing registers (coordinates) . commands: trapright draw s right triangle. trapleft draw s left triangle. drawvertex2i (format7) 31 24 23 16 15 0 drawvertex2i command reserved vertex xdc 0 ydc 0 the drawvertex2i command draws high - speed 2d t riangle it start s triangle drawing after setting parameters at 2dtriangle draw ing registers. commands: trianglefan draw s high - speed 2d t riangle. flagtrianglefan draw s high - speed 2dtriangle for polygon drawing in the flag buffer . drawvertex2ip (format7) 31 24 23 16 15 0 drawvertex2ip com mand reserved vertex ydc xdc the drawvertex2ip command draws high - speed 2d t riangle it start s drawing after setting parameters at 2dtriangle draw ing registers only the packed integer format can be used for vertex coordinates. commands: trianglefan draw hi gh - speed 2d t riangle. flagtrianglefan draw s high - speed 2dtriangle for polygon drawing in the flag buffer .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 122 specifications rev. 1.1 drawrectp (format5) 31 24 23 16 15 0 drawrectp command reserved rys rxs rsizey rsizex the drawrectp command fills rec tangle . the rectangle is filled with the current color after setting parameters at the rectangle registers. commands: bltfill fill s rectangle with current color (single). clearpolyflag fill s polygon drawing flag buffer area with 0. the size of drawing f rame is defined in rsizex,y. drawbitmapp (format6) 31 24 23 16 15 0 drawbitmapp command count rys rxs rsizey rsizex (pattern 0) (pattern 1) (pattern n) the drawbitmapp command draws rectangle patterns. commands: bltd raw draw s rectangle of 8 bits/pixel or 16 bits/pixel. drawbitmap draw s binary bitmap character pattern. bit 0 is drawn in transparent or background color, and bit 1 is drawn in foreground color. drawbitma plargep (format11) 31 24 23 16 15 0 drawbitmap large p command reserved count rys rxs rsizey rsizex (pattern 0) (pattern 1) (pattern n) the drawbitmapp command draws rectangle patterns. the parameter(count field) could be used up to 32 - bit(*1) unlike drawbitmapp. (*1 : the data format of counter field is signed long. thus actually it is possible to use up to 31 - bit.) commands: bltdraw draw s rectangle of 8 bits/pixel or 16 bits/pixel.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 123 specifications rev. 1.1 bltcopyp (format5) 31 24 23 16 15 0 bltcopyp command res erved srys srxs drys drxs brsizey brsizex the bltcopyp command copies rectangle pattern within drawing frame . commands: topleft start s bitblt transfer from top left coordinates . topright start s bitblt transfer from top right coordinates . bottomleft s tart s bitblt transfer from bottom left coordinates . bottomright start s bitblt transfer from bottom right coordinates . bltcopyalternatep (format5) 31 24 23 16 15 0 bltcopyalternatep command reserved saddr sstride srys srxs d addr dstride drys drxs brsizey brsizex the bltcopyalternatep command copies rectangle between two separate drawing frames . command: topleft start s bitblt transfer from top left coordinates .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 124 specifications rev. 1.1 blt copyaltalphablend p (format5) 31 24 23 16 1 5 0 bltcopyalternatep command reserved saddr sstride srys srxs blendstride blendrys blendrxs drys drxs brsizey brsizex the blt copyaltalphablend p command performs alpha blending for the source (specified using saddr, sstride, srxs, s rxy) and the alpha map (specified using abr (alpha base address), blendstride, blendrxs, blendrys) and then copies the result of the alpha blending to the destination (specified using fbr (frame buffer base address), xres (x resolution), drxs, and drys). command: reserved set 0000_0000 to maintain future compatibility.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 12 5 specifications rev. 1.1 10 register 10.1 register list 10.1.1 host interface register list base = hostbase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dtc 000 dtc dst drm dsu 004 dst drm dna dam dbm dw lts dts 008 lts dts lsta 010 lsta drq 018 drq ist 020 ist imask 024 imask srst 02c srst ccf 038 cge cot lsa 040 lsa lco 044 lco lreq 048 lreq rsw 05c rsw 0f0 cid
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 126 specifications rev. 1.1 cn ver
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 127 specifications rev. 1.1 10.1.2 graphics memory interface register list base = hostbase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mmr fffc twr id trrd trc trp tras trcd lowd rts saw asw cl
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 128 specifications rev. 1.1 10.1.3 display controller register list base = displaybase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dce (display controller enable) dcm (display control mode) 000 den l45e l23e l1e l0e cks dcs sc eeq sf esy sync dcee (display controller extend enable) dcem(display control extend mode) 100 den l5e l4e l3e l2e l1e l0e cks dcs sc eeq ede eof eod sf esy sync 004 htp (h total pixels) 008 hdb (h display bound ary) hdp (h display period) 00c vsw hsw hsp (h sync pulse position) 010 vtr (v total rasters) 014 vdp (v display period) vsp (v sync pulse position) 018 wy (window y) wx (window x) 01c wh (window heigh t) ww (window width) l0m (l0 mode) 020 l0c l0s (l0 width) l0h (l0 height) 024 l0oa (l0 origin address) 028 l0da (l0 display address) 02c l0dy (l0 display y ) l0dx (l0 display x) l0em (l0 extend mode) 110 l0ec l0pb l0wp 114 l0wy (l0 window y) l0wx (l0 window x) 118 l0wh (l0 window height) l0ww (l0 window width) l1m (l1 mode) 030 l1c l1yc l1cs l1im l1s (l1 width) 034 l1da (l1 display address) l1em (l1 extend mode) 1 20 l1ec l1pb l2m (l2 mode) 040 l2c l2flp l2s (l2 width) l2h (l2 height) 044 l2oa0 (l2 origin address 0) 048 l2da0 (l2 display address 0) 04c l2oa1 (l2 origin address 1) 050 l2da1 (l2 display address 1) 054 l2dy (l2 display y ) l2dx (l2 display x) l2em (l2 extend mode) 130 l2ec l2pb l2om l2wp 134 l2wy (l2 window y) l2wx (l2 window x) 138 l2wh (l2 window height) l2ww ( l2 window width)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 129 specifications rev. 1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 l3m (l3 mode) 058 l3c l3flp l3s (l3 width) l3h (l3 height) 05c l3oa0 (l3 origin address 0) 060 l3da0 (l3 display add ress 0) 064 l3oa1 (l3 origin address 1) 068 l3da1 (l3 display address 1) 06c l3dy (l3 display y ) l3dx (l3 display x) l3em (l3 extend mode) 140 l3ec l3pb l3om l3wp 144 l3wy (l3 window y) l3wx (l3 wi ndow x) 148 l3wh (l3 window height) l3ww (l3 window width) l4m (l4 mode) 070 l4c l4flp l4s (l4 width) l4h (l4 height) 074 l4oa0 (l4 origin address 0) 078 l4da0 (l4 display address 0) 07c l4oa1 (l4 origin address 1) 080 l4da1 (l4 display address 1) 084 l4dy (l4 display y ) l4dx (l4 display x) l4em (l4 extend mode) 150 l4ec l4om l4wp 154 l4wy (l4 window y) l4wx (l4 window x) 158 l4wh (l4 window height) l4 ww (l4 window width) l5m (l5 mode) 088 l5c l5flp l5s (l5 width) l5h (l5 height) 08c l5oa0 (l5 origin address 0) 090 l5da0 (l5 display address 0) 094 l5oa1 (l5 origin address 1) 098 l5da1 (l5 display address 1) 09c l5dy (l5 display y ) l5x (l5 display x) l5em (l5 extend mode) 160 l5ec l5om l5wp 164 l5wy (l5 window y) l5wx (l5 window x) 168 l5wh (l5 window height) l5ww (l5 window width)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 130 specifications rev. 1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cpm cutc (cursor transparent control) 0a0 cue1 cue0 cuo1 cuo0 cuzt cutc 0a4 cuoa0 (cursor0 origin address) 0a8 cuy0 (cursor0 position y) cux0 (cur sor0 position x) 0ac cuoa1 (cursor1 origin address) 0b0 cuy1 (cursor1 position y) cux1 (cursor1 position x) dls (display layer select) 180 dls5 dls4 dls3 dls2 dls1 dls0 184 dbgc (display back ground color) l0bld (l 0 blend) 0b4 l0be l0bs l0bi l0bp l0br l1bld (l1 blend) 188 l1be l1bs l1bi l1bp l1br l2bld (l2 blend) 18c l2be l2bs l2bi l2bp l2br l3bld (l3 blend) 190 l3be l3bs l3bi l3bp l3br l4bld (l4 blend) 194 l4be l4bs l4bi l4bp l4br l5bld (l5 blend) 198 l5be l5bs l5bi l5br
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 131 specifications rev. 1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 l0tc (l0 transparent control) 0bc l0zt l0tc (l0 transparent color) l2tr (l2 transparent control) l3tr (l3 transparent control) 0c0 l2zt l2tc (l2 transparent color) l3zt l3tr (l3 transparent color) l0tec (l0 extend transparency cont rol) 1a0 l0ezt l0etc (l0 extend transparent color) l1tec (l1 transparent extend control) 1a4 l1ezt l1etc (l1 extend transparent color) l2tec (l2 transparent extend control) 1a8 l2ezt l2etc (l2 extend transparent color) l3tec ( l3 transparent extend control) 1ac l3ezt l3etc (l3 extend transparent color) l4etc (l4 extend transparent control) 1b0 l4ezt l4etc (l4 extend transparent color) l5etc (l5 extend transparent control) 1b4 l5ezt l5etc (l5 extend trans parent color)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 132 specifications rev. 1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 l0pal0 400 a r g b 404 l0pal1 : : 7fc l0pal255 l1pal0 800 a r g b 804 l1pal1 : : bfc l1pal255 l2pal0 1000 a r g b 1004 l2pal1 : : 13fc l2pal255 l3pal0 1400 a r g b 1404 l3pal1 : : 17fc l3pal255
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 133 specifications rev. 1.1 10.1.4 drawing engine register list the parenthesized value in the offset field denotes the absolute address used by the setregister co mmand. base = drawbase offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ys 000 (000) s s s s int frac xs 004 (001) s s s s int frac dxdy 008 (002) s s s s int frac xus 00c (003) s s s s int frac dxudy 010 (004) s s s s int frac xls 014 (005) s s s s int frac dxldy 018 (006) s s s s int frac usn 01c (007) 0 0 0 0 int 0 lsn 020 (008) 0 0 0 0 int 0 rs 040 (010) 0 0 0 0 0 0 0 0 int frac drdx 044 (011) s s s s s s s s int frac drdy 048 (012 ) s s s s s s s s int frac gs 04c (013) 0 0 0 0 0 0 0 0 int frac dgdx 050 (014) s s s s s s s s int frac dgdy 054 (015) s s s s s s s s int frac bs 058 (016) 0 0 0 0 0 0 0 0 int frac dbdx 05c (017) s s s s s s s s int frac dbdy 060 (018) s s s s s s s s int frac
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 134 specifications rev. 1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 zs 080 (020) 0 int frac dzdx 084 (021) s int frac dzdy 088 (022) s int frac ss 0c0 (030) s s s int frac d sdx 0c4 (031) s s s int frac dsdy 0c8 (032) s s s int frac ts 0cc (033) s s s int frac dtdx 0d0 (034) s s s int frac dtdy 0d4 (035) s s s int frac qs 0d8 (036) 0 0 0 0 0 0 0 int frac dqdx 0dc (037) s s s s s s s int frac dqdy 0e0 (038) s s s s s s s int frac lpn 140 (050) 0 0 0 0 int 0 lxs 144 (051) s s s s int frac lxde 148 (052) s s s s s s s s s s s s s s s int frac lys 14c (053) s s s s int frac lyde 150 (054) s s s s s s s s s s s s s s s int frac lzs 154 (055) s int frac lzde 158 (056) s int frac
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 135 specifications rev. 1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pxdc 180 (060) 0 0 0 0 0 int 0 pydc 184 (061) 0 0 0 0 int 0 pzdc 188 (062) 0 int 0 rxs 200 (080) 0 0 0 0 int 0 rys 204 (08 1) 0 0 0 0 int 0 rsizex 208 (082) 0 0 0 0 int 0 rsizey 20c (083) 0 0 0 0 int 0 saddr 240 (090) 0 0 0 0 0 0 0 address sstride 244 (091) 0 0 0 0 int 0 srxs 248 (092) 0 0 0 0 int 0 srys 24c (093) 0 0 0 0 int 0 daddr 250 (094) 0 0 0 0 0 0 0 address dstride 254 (095) 0 0 0 0 int 0 drxs 258 (096) 0 0 0 0 int 0 drys 25c (097) 0 0 0 0 int 0 brsizex 260 (098) 0 0 0 0 int 0 brsizey 264 (099) 0 0 0 0 int 0 tcolor 280 (09a) 0 color pnbpi 28c (0a3) pn
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 136 specifications rev. 1.1 offse t 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 blpo 3e0 (0f8) bcr ctr 400 (100) fd fe ce fcnt nf ff fe ss ds ps ifsr 404 ( - ) nf ff fe ifcnt 408 ( - ) fcnt sst 40c ( - ) ss ds 410 ( - ) ds pst 414 ( - ) ps est 418 ( - ) fd ce mdr0 42 0 (108) zp cf cy cx bsv bsh mdr1/mdr1s/mdr1b 424 (109) lw bp bl log bm zw zcl zc mdr2/mdr2s/mdr2tl 428 (10a) tt log bm zw zcl zc as sm mdr3 42c (10b) ba tab tbl tws twt tf tc mdr4 430 (10c) log bm te mdr7 43c (10f) lth ez gg pgh pth pzh
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 137 specifications rev. 1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fbr 440 (110) fbase xres 4 44 (111) xres zbr 448 (112) zbase tbr 44c (113) tbase pfbr 450 (114) pfbase cxmin 454 (115) clipxmin cxmax 458 (116) clipxmax cymin 45c (117) clipymin cymax 460 (118) clipymax txs 464 (119) txsn txsm tis 468 (11a) tisn tism toa 46c (11b) xbo sho 470 (11c) shoffs abr 474 (11d) abase fc 480 (120) fgc8/16 bc 484 (121) bgc8/16 alf 488 (122) a 48c (123) blp tbc 494 (125) bc8/16
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 138 specifications rev. 1.1 offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 l x0dc 540 (150) 0 0 0 0 int 0 ly0dc 544 (151) 0 0 0 0 int 0 lx1dc 548 (152) 0 0 0 0 int 0 ly1dc 54c (153) 0 0 0 0 int 0 x0dc 580 (160) 0 0 0 0 int 0 y0dc 584 (161) 0 0 0 0 int 0 x1dc 588 (162) 0 0 0 0 int 0 y1dc 58c (163) 0 0 0 0 int 0 x2dc 590 (16 4) 0 0 0 0 int 0 y2dc 594 (165) 0 0 0 0 int 0
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 139 specifications rev. 1.1 10.1.5 geometry engine register list the parenthesized value in the offset field denotes the absolute address used by the setregister command. base = geometrybase offset 31 30 29 28 27 26 25 24 23 22 21 2 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gctr 000 ( - ) fo fcnt nf ff fe gs ss ps gmdr0 040 (2010) cf df st z c f gmdr1 044 (2011) bo ep aa gmdr1e - po lv t c bc uw bm tm bp sp bo ep aa gmdr2 048 (2012) fd cf gmdr2e - tl sp fd cf 400 ( - ) dfifog
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 140 specifications rev. 1.1 10.2 explanation of register terms appeared in this chapter are explained below: 1. register add ress indicates address of register 2. bit number indicates bit number 3. bit field name indicates name of each bit field included in register 4. r/w indicates access attribute (read/write) of each field each symbol shown in this section denotes the following: r0 ?0? always read at read. write access is don?t care. w0 only ?0? can be written . r read enable d w write enable d rx read enable d (read values undefined) rw read and write enable d rw0 read and write 0 enable d 5. initial value indicates initial value of i mmediately before the reset of each bit field. 6. handling of reserved bits ? 0 ? is recommended for the write value so that compatibility can be maintained with future products.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 141 specifications rev. 1.1 10.2.1 host interface registers dtc (dma transfer count) register address hostbasea ddress + 00 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved dtc r/w r0 rw initial value 0 don?t care dtc is a readable /writable 32 - bit register which set s the transfer count in either one long - word (32 bits) or 32 bytes units. when ?1h? is set transfer is performed once . however, when ?0h? is set, it indicates the maximum transfer count and 16m (16,777,216) data are transferred. during dma transfer, the remaining transfer coun t is shown, therefore, the register value cannot be overwritten until dma transfer is completed. note: this register need not be set in a mode in which dual dma ack is not used, or the v832 mode. dsu (dma set up) register address hostbaseaddress + 04 h bit number 7 6 5 4 3 2 1 0 bit field name reserved dam dbm dw r/w r0 rw rw rw initial value 0 0 0 0 bit 0 dw (dma word) specifies dma transfer count 0: 1 - double word (32 bits ) per dma transfer 1: 8 - double word s (32 bytes ) per dma transfer (only sh4) dbm (dma bus request mode) selects dreq mode used in dma transfer in dual - address mode 0: dreq is not negated during dma transfer irrespective of cycle steal or burst mode . bit 1 1: dreq is negated irrespective of cycle steal or burst mode when c oral cannot receive data (that is, when ready cannot be returned immediately). when coral is ready to receive data, dreq is reasserted (when dma transfer is performed in the single - address mode, dreq is controlled automatically). bit 2 dam (dma address m ode) selects dma address mode in issuing external request 0: dual address mode 1: single address mode (sh4 only) bit 3 dna (dual address no ack mode) this bit is selected when using the dual - address - mode dma that does not use the ack signal. 0: us es dual - address - mode dma that uses ordinary ack signal 1: uses dual - address - mode dma that does not use ack signal detection of the dreq edge is supported; dreq is negated per transfer. when data cannot be received irrespective of the bit1 setting, dreq continues being negated.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 142 specifications rev. 1.1 drm (dma request mask) register address hostbaseaddress + 05 h bit number 7 6 5 4 3 2 1 0 bit field name reserved drm r/w r0 rw initial value 0 0 this register enables the dma request. setting ?1? to this register to tempor arily stop the dma request from the coral . the external request is enabled by setting ?0? to this register. dst (dma status) register address hostbaseaddress + 06 h bit number 7 6 5 4 3 2 1 0 bit field name reserved dst r/w r0 r initial value 0 0 thi s register indicates the dma transfer status. dst is set to ?1? during dma transfer. this state is cleared to ?0? when the dma transfer is completed. dts (dma transfer stop) register address hostbaseaddress + 08 h bit number 7 6 5 4 3 2 1 0 bit field na me reserved dts r/w r0 rw initial value 0 0 this register suspends dma transfer. an ongoing dma transfer is suspended by setting dts to ?1?. in the dual - address without ack mode, to end the dma transfer, write ? 1 ? to this register after cpu dma transfer . lts (display transfer stop) register address hostbaseaddress + 09 h bit number 7 6 5 4 3 2 1 0 bit field name reserved lts r/w r0 rw initial value 0 0 this register suspends displaylist transfer. ongoing displaylist transfer is suspended by setting lts to ?1?. lsta (displaylist transfer status) register address hostbaseaddress + 10 h bit number 7 6 5 4 3 2 1 0 bit field name reserved lsta r/w r0 r initial value 0 0 this register indicates the displaylist transfer status from graphics memory. ls ta is set to ?1? while displaylist transfer is in progress. this status is cleared to 0 when displaylist transfer is completed
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 143 specifications rev. 1.1 drq (dma reqquest) register address hostbaseaddress + 18 h bit number 7 6 5 4 3 2 1 0 bit field name reserved drq r/w r0 rw 1 initial value 0 0 this register starts sending external dma request . dma transfer using the external request handshake is triggered by setting drq to ?1?. the external dreq signal can not be issued when dma is masked by the drm register. this register cannot be written ?0?. when dma transfer is completed, this status is cleared to ?0?. ist (interrupt status) register address hostbaseaddress + 20 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit fie ld name reserved resv reserved ist ist r/w r0 r 0w0 r0 rw0 r w0 initial value 0 0 0 0 0 this register indicates the current interrupt status. it shows that an interrupt request is issued when ? 1 ? is set to this register. the interrupt status is cleared by writing ?0? to this register. bit 0 cerr (command error flag) indicates drawing command execution error interrupt bit 1 cend (command end) indicates drawing command end interrupt bit 2 vsync (vertical sync.) indicates vertical interrupt synchronizati on bit 3 fsync (frame sync.) indicates frame synchronization interrupt bit 4 syncerr (sync. error) indicates external synchronization error interrupt bit 17 and 16 reserved this field is provided for testing. normally, the read value is ? 0 ? , but note th at it may be ? 1 ? when a drawing command error (bit 0) has occurred.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 144 specifications rev. 1.1 im ask (interrupt mask) register address hostbaseaddress + 24 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved resv reserved imask imask r/w r0 r0 w0 r0 rw rw initial value 0 0 0 0 0 this register masks interrupt requests. even when the interrupt request is issued for the bit to which ? 0 ? is written, interrupt signal is not asserted for cpu. bit 0 cerrm (comma nd error interrupt mask) masks drawing command execution error interrupt bit 1 cendm (command interrupt mask) masks drawing command end interrupt bit 2 vsyncm (vertical sync. interrupt mask) masks vertical synchronization interrupt bit 3 fsynch (frame s ync. interrupt mask) ma s ks frame synchronization interrupt bit 4 syncerrm ( sync error mask ) masks external synchronization error interrupt srst (software reset) register address hostbaseaddress + 2c h bit number 7 6 5 4 3 2 1 0 bit field name reserved srst r/w r0 w1 initial value 0 0 this register controls software reset. when ?1? is set to this register, a software reset is performed .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 145 specifications rev. 1.1 lsa (displaylist source address) register address hostbaseaddress + 40 h bit number 31 30 29 28 27 26 25 24 23 2 2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved lsa r/w r0 rw r0 initial value 0 don?t care 0 this register sets the displaylist transfer source address. when displaylist is transferred from graphics memory, set the t ransfer start address of displaylist stored in graphics memory . since the low er two bits of this register are always treated as ?0?, displaylist must be 4 - byte aligned. the value s set at this register do not change during or after transfer . lco (displayl ist count) register address hostbaseaddress + 44 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved lco r/w r0 rw initial value 0 don?t care this register sets the displaylist tra nsfer count. set the display list transfer count by the long word. when ?1 h ? is set, 1 - word data is transferred. when ?0? is set, it is considered to be the maximum count and 16m (16,777,216) words of data are transferred. the values set at this registe r do not change during or after transfer . lreq (displaylist transfer request) register address hostbaseaddress + 48 h bit number 7 6 5 4 3 2 1 0 bit field name reserved lreq r/w r0 rw1 initial value 0 0 this register triggers displaylist transfer from the graphics memory. transfer is started by setting lreq to ?1?. the displaylist is transferred from the graphics memory to the internal display list fifo. access to the display list fifo by the cpu or dma is disabled during transfer.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 146 specifications rev. 1.1 rsw (register lo cation switch) register address hostbaseaddress + 5c h bit number 7 6 5 4 3 2 1 0 bit field name reserved rsw r/w r0 rw initial value 0 0 in sh3 or sh4 mode, set this register when moving the register area from the center (1fc0000) to the end of the c oral area (3fc0000). this move can be performed when ? 1 ? is written to this register. set this register at the first access after reset. access coral a fter about 20 bus clocks after setting the register. cid (chip id register) register address hostbasea ddress + f0 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cn ver r/w r0 r r initial value 0 0000_0011 0 this is the chip identification register. bit 7 to 0 ver ( version ) t his field indicates the chip ? s unique version number. note that the unique version number for the es version and that of the mass - produced version are different. 0000_0000 es 0000_0001 reserved 0000_0010 reserved for lq others reserved bit 15 to 8 cn ( chip name ) this field indicates the chip name. 0000_0000 reserved 0000_0001 reserved 0000_0010 reserved 0000_0011 coral others reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 147 specifications rev. 1.1 ccf (change of clock frequency) register address hostbaseaddress + 38 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cge cot reserved r/w rw0 rw rw rw0 initial value 0 00 00 0 this register change s the operating frequency. bit 19 and 18 cge (clock select for geometry en gine ) selects the clock for the geometry engine 11 reserved 10 166 mhz 01 133 mhz 00 100 mhz bit 17 and 16 cot (clock select for the others except - geometry engine) selects the clock for other than the geometry engine 11 reserved 10 rese rved 01 133 mhz 00 100 mhz notes: 1. write ? 0 ? to the bit field other than the above ([31:20], [15:00]). 2. operation is not as sured when the clock setting relationship is cge < cot.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 148 specifications rev. 1.1 10.2.2 graphics memory interface registers mmr (memory i/f mode registe r) register address hostbaseaddress + fffc h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name *1 twr reserved *1 *1 trrd trc trp tras trcd lowd rts raw asw cl r/w rw rw r r1 w0 r rw rw rw rw rw rw rw rw rw rw initial value 0 0 don ? t care 1 0 00 0000 00 000 00 00 000 000 0 000 *1: reserved this register sets the mode of the graphics memory interface. a value must be written to this register after a reset. ( when default setting is performed , a value must also be written to this register.) only write once to this register; do not change the written value during operation. this register is not initialized at a software reset. bit 2 to 0 cl (cas latency) sets the cas latency. write the sam e value as this field, to the mode register for sdram 011 cl3 010 cl2 other than the above setting disabled bit 3 asw (attached sdram bit width) sets the bit width of the data bus (memory bus width mode) 1 64 bit 0 32 bit bit 6 to 4 saw (sdram address width) sets the bit width of the sdram address 001 15 bit bank 2 bit row 13 bit col 9 bit sdram 111 14 bit bank 2 bit row 12 bit col 9 bit sdram 110 14 bit bank 2 bit row 12 bit col 8 bit sdram 101 13 bit bank 2 bit row 11 bit col 8 bit sdram 100 12 bit bank 1 bit row 11 bit col 8 bit fcram 000 14 bit bank 2 bit row 12 bit col 8 bit sdram other than the above setting disabled bit 9 to 7 rts (refresh timing setting) sets the refresh interval 000 refresh is performed ev ery 384 internal clocks. 111 refresh is performed every 1552 internal clocks. 001 to 110 refresh is performed every ? 64 n ? internal clocks in the 64 to 384 range.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 149 specifications rev. 1.1 bit 11 and 10 lowd sets the count of clocks secured for the period from the insta nt the ending data is output to the instant the write command is issued. 10 2 clocks 00 2 clocks other than the above setting disabled bit 13 and 12 trcd sets the wait time secured from the bank active to cas. the clock count is used to expres s the wait time. 11 3 clocks 10 2 clocks 01 1 clock 00 0 clock bit 16 to 14 tras sets the minimum time for 1 bank active. the clock count is used to express the minimum time. 111 7 clocks 110 6 clocks 101 5 clocks 100 4 clocks 011 3 clocks 010 2 clocks other than the above setting disabled bit 18 and 17 trp sets the wait time secured from the pre - charge to the bank active. the clock count is used to express the wait time. 11 3 clocks 10 2 clocks 01 1 clock bit 2 2 to 19 trc this field sets the wait time secured from the refresh to the bank active. the clock count is used to express the wait time. 1010 10 clocks 1001 9 clocks 1000 8 clocks 0111 7 clocks 0110 6 clocks 0101 5 clocks 0100 4 clocks
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 150 specifications rev. 1.1 0 011 3 clocks other than the above setting disabled bit 24 and 23 trrd sets the wait time secured from the bank active to the next bank active. the clock count is used to express the wait time. 11 3 clocks 10 2 clocks bit 26 reserved alw ays write ? 0 ? at write . ? 1 ? is always read at read. bit 30 twr sets the write recovery time (the time from the write command to the read or to the pre - charge command). 1 2 clocks 0 1 clock
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 151 specifications rev. 1.1 10.2.3 display control register dcm (display control mode ) / dcem (display control extend mode) register address displaybaseaddress + 00 h (displaybaseaddress + 100 h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name cks reserve d sc eeq ode reserve d reserve d sf esy sync r/w rw rw0 rw rw rw rx rx rw rw rw 01110 (dcm) initial value 0 0 11101 (dcem) 0 x 0 1 00 this register controls the display count mode. it is not initialized by a software reset. this register is mapped to two addresses. the difference between the two registers is th e format of the frequency division rate setting ( sc ) . bit 1 to 0 sync (synchronize) set synchronization mode x0 non - interlace mode 10 interlace mode 11 interlace video mode bit 2 esy (external synchronize) sets external synchronization mode 0: external synchronization disable d 1: external synchronization enable d bit 3 sf (synchronize signal format) sets format of synchronization (vsync, hsync) signals 0: negative logic 1: positive logic bit 7 eeq (enable equalizing pulse) sets ccync signal mode 0: does not insert equalizing pulse into ccync signal 1: inserts equalizing pulse into ccync signal bit 13 to 8 sc (scaling) divides display reference clock by the preset ratio to generate dot clock offset = 0 offset = 10 0 h x 00000 frequency not divided 000000 frequency not divided x 00001 frequency division rate = 1/ 4 000001 frequency division rate = 1/2 x 00010 frequency division rate = 1/ 6 000010 frequency division rate = 1/3 x00011 frequency division rate = 1/8 00 0011 frequency division rate = 1/4 : : x 11111 frequency division rate = 1/64 111111 frequency division rate = 1/64
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 152 specifications rev. 1.1 when n is set, with offset = 0, the frequency division rate is 1/(2n + 2). when m is set, with offset = 100h, the frequency divisi on rate is 1/(m + 1). basically , these are setting parameters with the same function ( 2n + 2 = m + 1 ) . because of this, m = 2n + 1 is established. when n is set to the sc field with offset = 0, 2n + 1 is reflected with offset = 100h. also, when pll is selected as the reference clock, frequency division rates 1/1 to 1/5 are non - functional even when set; other frequency division rates are assigned. bit 15 cks (clock source) selects reference clock 0: internal pll output clock 1: dclki input
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 153 specifications rev. 1.1 dce (display controller enable) register address displaybaseaddress + 02 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name den reserved l45e l23e l1e l0e r/w rw r0 rw rw rw rw initial value 0 0 0 0 0 0 this register controls enabling t he video signal output and display of each layer. layer enabling is specified in four - layer units to maintain backward compatibility with previous products. bit 0 l0e ( l0 layer enable ) enables display of the l0 layer. the l0 layer corresponds to the c layer for previous products. 0: does not display l0 layer 1: displays l0 layer bit 1 l1e ( l1 layer enable ) enables display of the l1 layer. the l1 layer corresponds to the w layer for previous products. 0: does not display l1 layer 1: displ ays l1 layer bit 2 l23e ( l2 & l3 layer enable ) enables simultaneous display of the l2 and l3 layers. these layers correspond to the m layer for previous products. 0: does not display l2 and l3 layer 1: displays l2 and l3 layer bit 3 l45e ( l4 & l5 layer enable ) enables simultaneous display of the l4 and l5 layers. these layers correspond to the b layer for previous products. 0: does not display l4 and l5 layer 1: displays l4 and l5 layer bit 15 den (display enable) enables display 0: does not output display signal 1: outputs display signal
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 154 specifications rev. 1.1 dce e (display controller extend enable) register address displaybaseaddress + 1 02 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name den reserved l5e l4e l3e l2e l1e l0e r/w rw r0 rw rw rw rw rw rw initial value 0 0 0 0 0 0 0 0 this register controls enabling the video signal output and display of each layer. this register has the same function as dce. bit 0 l0e ( l0 layer enable ) enables l0 layer display 0: does no t display l0 layer 1: displays l0 layer bit 1 l1e ( l1 layer enable ) enables l1 layer display 0: does not display l1 layer 1: displays l1 layer bit 2 l2e ( l2 layer enable ) enables l2 layer display 0: does not display l2 layer 1: displa ys l2 layer bit 3 l3e ( l3 layer enable ) enables l3 layer display 0: does not display l3 layer 1: displays l3 layer bit 4 l4e ( l4 layer enable ) enables l4 layer display 0: does not display l4 layer 1: displays l4 layer bit 5 l5e ( l5 layer enable ) enables l5 layer display 0: does not display l5 layer 1: displays l5 layer bit 15 den ( display enable ) enables display 0: does not output display signal 1: outputs display signal
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 155 specifications rev. 1.1 htp (horizontal total pixels) register addres s displaybaseaddress + 06 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved htp r/w r0 rw initial value 0 don?t care this register controls the horizontal total pixel count. setting value + 1 is the total pixel count. hdp (ho rizontal display period) register address displaybaseaddress + 08 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hdp r/w r0 rw initial value 0 don?t care this register controls the total horizontal display period in unit of pixel clock s . setting value + 1 is the pixel count for the display period. hdb (horizontal display boundary) register address displaybaseaddress + 0a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hdb r/w r0 rw initial val ue 0 don?t care this register controls the display period of the left part of the window in unit of pixel clocks. setting value + 1 is the pixel count for the display period of the left part of the window . when the window is not divided into right and l eft before display, set the same value as hdp. hsp (horizontal synchronize pulse position) register address displaybaseaddress + 0c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved hsp r/w r0 rw initial value 0 don?t care thi s register controls the pulse position of the horizontal synchronization signal in unit of pixel clock s . when the clock count since the start of the display period reaches s etting value + 1, the horizontal synchronization signal is asserted. hsw (horizont al synchronize pulse width) register address displaybaseaddress + 0e h bit number 7 6 5 4 3 2 1 0 bit field name hsw r/w rw initial value don?t care this register controls the pulse width of the horizontal synchronization signal in unit of pixel clock s . setting value + 1 is the pulse width clock count.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 156 specifications rev. 1.1 vsw (vertical synchronize pulse width) register address displaybaseaddress + 0f h bit number 7 6 5 4 3 2 1 0 bit field name reserved vsw r/w r0 rw initial value 0 don?t care this register controls the pulse width of vertical synchronization signal in unit of raster. setting value + 1 is the pulse width raster count. vtr (vertical total rasters) register address displaybaseaddress + 12 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vtr r/w r0 rw initial value 0 don?t care this register controls the vertical total raster count. setting value + 1 is the total raster count. for the interlace display, setting value + 1.5 is the total raster count for 1 field; 2 setti ng value + 3 is the total raster count for 1 frame (see section 8.3.2 ). vsp (vertical synchronize pulse position) register address displaybaseaddress + 14 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vsp r/w r0 rw initial value 0 don?t care this register controls the pulse position of vertical synchronization signal in unit of raster. the vertical synchronization pulse is asserted starting at the s etting value + 1 st raster relative to the display start raster. vdp (vertic al display period) register address displaybaseaddress + 16 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved vdp r/w r0 rw initial value 0 don?t care this register controls the vertical display period in unit of raster. sett ing value + 1 is the count of raster to be displayed.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 157 specifications rev. 1.1 l0m ( l0 layer mode ) register address displaybaseaddress + 20 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l0c reserved reserved low reserved ch r/w rw r0 r0 rw r0 rw initial value 0 0 0 don?t care 0 don?t care bit 11 to 0 l0h ( l0 layer height ) specifies the height of the logic frame of the l0 layer in pixel units. setting value + 1 is the height bit 23 to 16 l0w ( l0 layer m emory width ) sets the memory width (stride) of the logic frame of the l0 layer in 64 - byte units bit 31 l0c ( l0 layer color mode ) sets the color mode for l0 layer 0 indirect color (8 bits/pixel) mode 1 direct color (16 bits/pixel) mode l0em ( l0 - layer extended mode ) register address displaybaseaddress + 110 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----- 4 3 2 1 0 bit field name l0ec reserved l0pb reserved l0wp r/w rw r0 rw r0 rw initial value 0 0 0 bit 0 l0 wp ( l0 layer window position enable ) selects the display position of l0 layer 0 compatibility mode display (c layer supported) 1 window display bit 23 to 20 l0pb ( l0 layer palette base ) shows the value added to the index when subtracting palette of l0 layer. 16 times of setting value is added. bit 31 and 30 l0ec ( l0 layer extended color mode ) sets extended color mode for l0 layer 00 mode determined by l0c 01 direct color (24 bits/pixel) mode 1x reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 158 specifications rev. 1.1 l0oa ( l0 layer origi n address ) register address displaybaseaddress + 24 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0oa r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the orig in address of the logic frame of the l0 layer. since lower 4 bits are fixed at ? 0 ? , address 16 - byte - aligned. l0da ( l0 - layer display address ) register address displaybaseaddress + 28 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0da r/w r0 rw initial value 0 don?t care this register sets the display origin address of the l0 layer. for the direct color mode (16 bits/pixel), the lower 1 bit is ? 0 ? , and this address is treated a s being aligned in 2 byte s. l0dx ( l0 - layer display position x ) register address displaybaseaddress + 2c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0dx r/w r0 rw initial value 0 don?t care this register sets the display starting position (x coordinates) of the l0 layer on the basis of the origin of the logic frame in pixel s. l0dy ( l0 - layer display position y ) register address displaybaseaddress + 2e h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserv ed l0dy r/w r0 rw initial value 0 don?t care this register sets the display starting position (y coordinates) of the l0 layer on the basis of the origin of the logic frame in pixel s.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 159 specifications rev. 1.1 l0wx ( l0 layer window position x ) register address displaybaseaddres s + 114 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0wx r/w r0 rw initial value 0 this register sets the x coordinates of the display position of the l0 layer window. l0wy ( l0 layer window position y ) register address d isplaybaseaddress + 116 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0wy r/w r0 rw initial value 0 this register sets the y coordinates of the display position of the l0 layer window. l0 ww ( l0 layer window width) registe r address displaybaseaddress + 118 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0 ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l0 layer w indow. do no t specify ?0?. l0 wh ( l0 layer window height) register address displaybaseaddress + 1 1a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction d isplay size ( height ) of the l0 layer window. setting value + 1 is the height.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 160 specifications rev. 1.1 l1m (l1 - layer mode) register address displaybaseaddress + 30 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 5 4 3 2 1 0 bit field name l 1c l1yc l1cs l1im reserve d l1w reserve d r/w rw rw rw rw r0 rw r0 initial value 0 0 0 0 0 don ? t care 0 bit 23 to 16 l1 w ( l1 layer memory width) set s the memory width (stride) of the logic frame of the l layer in unit of 64 byte s bit 28 l1 im ( l1 la yer interlace mode) sets video capture mode when l1 cs in capture mode 0: normal mode 1: for non - interlace display, displays captured video graphics in weave mode for interlace and video display, buffers are managed in frame units (pair of odd field a nd even field). bit 29 l1 cs ( l1 layer capture synchronize ) sets whether the layer is used as normal display layer or as video capture 0: normal mode 1: capture mode bit 30 l1 yc ( l1 layer yc mode) sets color format of l1 layer the yc mode mu st be set for video capture. 0: rgb mode 1: yc mode l1 c ( l1 layer color mode) sets color mode for l1 layer 0: indirect color (8 bits/pixel) mode bit 31 1: direct color (16 bits/pixel) mode
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 161 specifications rev. 1.1 l1em ( l1 layer extended mode ) register address displ aybaseaddress + 120 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 4 3 2 1 0 bit field name l1ec reserved l1pb reserved r/w rw r0 rw r0 initial value 0 0 0 0 bit 23 to 20 l1pb ( l1 layer palette base ) shows the v alue added to the index when subtracting palette of l1 layer. 16 times of setting value is added. bit 31 to 30 l1ec ( l1 layer extended color mode ) sets extended color mode for l1 layer 00 mode determined by l0c 01 direct color (24 bits/pixel) mo de 1x reserved l1da ( l1 layer display address ) register address displaybaseaddress + 34 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0da r/w r0 rw initial value 0 don?t ca re this register sets the display origin address of the l1 layer. for the direct color mode (16 bits/pixel), the lower 1 bit is ? 0 ? , and this register is treated as being aligned in 2 byte s. wraparound processing is not performed for the l1 layer, so th e frame origin linear address and display position (x coordinates, and y coordinates) are not specified. l1wx ( l1 layer window position x ) register address displaybaseaddress + 124 h (dispplaybaseaddress + 18 h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l1wx r/w r0 rw initial value 0 don?t care this register sets the x coordinates of the display position of the l1 layer window. this register is placed in two address spaces. the parenthesized address is the register addre ss to maintain compatibility with previous products. the same applies to l1wy, l1ww, and l1wh. l1wy ( l1 layer window position y ) register address displaybaseaddress + 126 h (dispplaybaseaddress + 1a h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l1wy r/w r0 rw initial value 0 don?t care this register sets the y coordinates of the display position of the l1 layer window.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 162 specifications rev. 1.1 l1ww ( l1 layer window width ) register address displaybaseaddress + 128 h (dispplaybaseaddress + 1c h ) bi t number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l1ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l1 layer w indow. do not specify ?0?. l1 wh ( l1 layer window hei ght) register address displaybaseaddress + 1 2a h (( displaybaseaddress + 1 e h ) bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l1 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l1 layer window. setting value + 1 is the height.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 163 specifications rev. 1.1 l2m ( l2 layer mode ) register address displaybaseaddress + 40 h bit number 31 30 29 28 27 - - 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l2c l2flp res erved l2w reserved l2h r/w rw rw r0 rw r0 rw initial value 0 00 0 don?t care 0 don?t care bit 11 to 0 l2h ( l2 layer height ) specifies the height of the logic frame of the l2 layer in pixel units. setting value + 1 is the height bit 23 to 16 l2w ( l2 layer memory width ) set s the memory width (stride) of the logic frame of the l2 layer in 64 - byte units bit 30 and 29 l2flp (l2 layer flip mode) set s flipping mode for l2 layer 00 display s frame 0 01 display s frame 1 10 switch es frame 0 an d 1 alternately for display 11 reserved bit 31 l2c ( l2 layer color mode ) sets the color mode for l2 layer 0 indirect color (8 bits/pixel) mode 1 direct color (16 bits/pixel) mode
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 164 specifications rev. 1.1 l2em ( l2 layer extended mode ) register address displaybaseaddr ess + 130 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----- 4 3 2 1 0 bit field name l2ec reserved l2pb reserved l2om l0wp r/w rw r0 rw r0 rw rw initial value 00 0 0 0 0 bit 0 l2 wp ( l2 layer window position enable ) selects the display position of l2 layer 0 compatibility mode display (ml layer supported) 1 window display bit 1 l2om (l2 layer overlay mode) selects the overlay mode for l2 layer 0 compatibility mode 1 extended mode bit 23 to 20 l2pb ( l2 layer palette base ) shows the value added to the index when subtracting palette of l2 layer. 16 times of setting value is added. bit 31 and 30 l2ec ( l2 layer extended color mode ) sets extended color mode for l2 layer 00 mode determined by l 2c 01 direct color (24 bits/pixel) mode 1x reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 165 specifications rev. 1.1 l 2 oa0 ( l2 layer origin address 0) register address displaybaseaddress + 44 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserv e d l 2 oa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 2 layer in frame 0 . since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. l 2 da0 (l 2 layer display address 0) register address displaybaseaddress + 48 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d l 2 da0 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 2 laye r in frame 0. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l 2 oa1 (l 2 layer origin address 1) register address displaybaseaddress + 4c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d l 2 oa1 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 2 layer in frame 1 . since lower 4 - bits are fixed to ?0?, this address is 16 - byte aligned. l 2 da1 (l 2 layer display address 1) register address displaybaseaddress + 50 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d l 2 da1 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 2 layer in frame 1. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l 2 dx (l 2 layer display position x) register address displaybaseaddress + 54 h bi t number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l 2 dx r/w r0 rw initial value 0 don?t care this register sets the display starting position (x coordinates) of the l2 layer on the basis of the origin of the logic frame in pixel s.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 166 specifications rev. 1.1 l 2 dy (l 2 layer display position y) register address displaybaseaddress + 56 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l 2 dy r/w r0 rw initial value 0 don?t care this register sets the display starting position (y coordi nates) of the l2 layer on the basis of the origin of the logic frame in pixel s. l2wx ( l2 layer window position x ) register address displaybaseaddress + 134 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l2wx r/w r0 rw initia l value 0 don?t care this register sets the x coordinates of the display position of the l2 layer window. l2wy ( l2 layer window position y ) register address displaybaseaddress + 136 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reser ved l2wy r/w r0 rw initial value 0 don?t care this register sets the y coordinates of the display position of the l2 layer window. l2 ww ( l2 layer window width) register address displaybaseaddress + 138 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l2 ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l2 layer window. do not specify ?0?. l2 wh ( l2 layer window height) register address displaybaseaddress + 1 3 a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l2 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l2 layer window. setting value + 1 is the height.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 167 specifications rev. 1.1 l3 m (l 3 layer mode) register address displaybaseaddress + 58 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l 3 c l 3 flp reserve d l 3 w reserve d l 3 h r/w rw r0 r0 rw r0 rw initial value 0 0 0 don?t care 0 don?t care bit 11 to 0 l3 h ( l3 layer height) specifies the height of the logic frame of the l3 layer in pixel units. setting value + 1 is the height bit 23 to 16 l3 w ( l3 layer memory width) set s the memory width (stride) of the logic fra me of the l3 layer in 64 - byte units bit 30 and 29 l3 flp ( l3 layer flip mode) set s flipping mode for l3 layer 00 display s frame 0 01 display s frame 1 10 switch es frame 0 and 1 alternately for display 11 reserved bit 31 l3 c ( l3 layer color mode) sets the color mode for l3 layer 0 indirect color (8 bits/pixel) mode 1 direct color (16 bits/pixel) mode
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 168 specifications rev. 1.1 l3em ( l3 layer extended mode ) register address displaybaseaddress + 140 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 4 3 2 1 0 bit field name l3ec reserved l3pb reserved l3om l3wp r/w rw r0 rw r0 rw rw initial value 00 0 0 0 0 0 bit 0 l3 wp ( l3 layer window position enable ) selects the display position of l3 layer 0 compatibility mode displ ay (mr layer supported) 1 window display bit 1 l3om (l3 layer overlay mode) selects the overlay mode for l3 layer 0 compatibility mode 1 extended mode bit 23 to 20 l3pb ( l3 layer palette base ) shows the value added to the index when subtr acting palette of l3 layer. 16 times of setting value is added. bit 31 and 30 l3ec ( l3 layer extended color mode ) sets extended color mode for l3 layer 00 mode determined by l3c 01 direct color (24 bits/pixel) mode 1x reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 169 specifications rev. 1.1 l3oa0 ( l3 lay er origin address 0 ) register address displaybaseaddress + 5c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3oa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register se ts the origin address of the logic frame of the l 3 layer in frame 0 . since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. l3da0 ( l3 layer display address 0 ) register address displaybaseaddress + 60 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3da0 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 3 layer in frame 0. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l3oa1 ( l3 layer origin address 1 ) register address displaybaseaddress + 64 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3oa1 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 3 layer in frame 1 . since lower 4 - bits are fixed to ?0?, this address is 16 - byte aligned. l3oa1 ( l3 layer display address 1 ) register address displayb aseaddress + 68 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3da1 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 3 layer in frame 1. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l3dx ( l3 layer display position x ) register address displaybaseaddress + 6c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3dx r/w r0 rw initial value 0 don?t care this register set s the display start ing position (x coordinate s ) of the l 3 layer on the basis of the origin of the logic frame in pixels .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 170 specifications rev. 1.1 l3dy ( l3 layer display position y ) register address displaybaseaddress + 6e h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3dy r/w r0 rw initial value 0 don?t care this register sets the display starting position (y coordinates) of the l3 layer on the basis of the origin of the logic frame in pixel s . l3wx ( l3 layer window position x ) register address displaybaseaddress + 144 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3wx r/w r0 rw initial value 0 don?t care this register sets the x coordinates of the display posi tion of the l3 layer window. l3wy ( l3 layer window position y ) register address displaybaseaddress + 146 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3wy r/w r0 rw initial value 0 don?t care this register sets the y coor dinates of the display position of the l3 layer window. l3 ww ( l3 layer window width) register address displaybaseaddress + 148 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3 ww r/w r0 rw initial value 0 don?t care this re gister controls the horizontal direction display size ( width ) of the l3 layer window. do not specify ?0?. l3 wh ( l3 - layer window height) register address displaybaseaddress + 1 4a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of the l3 layer window. setting value + 1 is the height.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 171 specifications rev. 1.1 l4m ( l4 layer mode ) register address displaybaseaddress + 70 h bit number 31 30 29 2 8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l4c l4flp reserved l4w reserved l4h r/w rw rw r0 rw r0 rw initial value 0 don?t care 0 don?t care bit 11 to 0 l4h ( l4 layer height ) specifies the height of the logic frame of the l4 layer in pixel units. setting value + 1 is the height bit 23 to 16 l4w ( l4 layer memory width ) set s the memory width ( stride ) logic frame of the l4 layer in 64 - byte units bit 30 and 29 l4flp (l4 layer flip mode) set s flipping mode for l4 layer 00 display s frame 0 01 display s frame 1 10 switch es frame 0 and 1 alternately for display 11 reserved bit 31 l4c ( l4 layer color mode ) sets the color mode for l4 layer 0 indirect color (8 bits/pixel) mode 1 dire ct color (16 bits/pixel) mode
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 172 specifications rev. 1.1 l4em ( l4 layer extended mode ) register address displaybaseaddress + 150 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 4 3 2 1 0 bit field name l4ec reserved l4om l4wp r/w rw r0 rw r0 rw rw initial value 00 0 0 0 0 0 bit 0 l4 wp ( l4 layer window position enable ) selects the display position of l4 layer 0 compatibility mode display (bl layer supported) 1 window display bit 1 l4om (l4 layer overlay mode) selects the overla y mode for l4 layer 0 compatibility mode 1 extended mode bit 23 to 20 l4pb ( l4 layer palette base ) shows the value added to the index when subtracting palette of l4 layer. 16 times of setting value is added. bit 31 and 30 l4ec ( l4 layer exte nded color mode ) sets extended color mode for l4 layer 00 mode determined by l4c 01 direct color (24 bits/pixel) mode 1x reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 173 specifications rev. 1.1 l4oa0 ( l4 layer origin address 0 ) register address displaybaseaddress + 74 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4oa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 4 layer in frame 0 . since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. l4da0 ( l4 layer display address 0 ) register address displaybaseaddress + 78 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4da0 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 4 layer in frame 0. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l4oa1 ( l4 layer origin address 1 ) register address displayb aseaddress + 7c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4oa1 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of th e l 4 layer in frame 1 . since lower 4 - bits are fixed to ?0?, this address is 16 - byte aligned. l4oa1 ( l4 layer display address 1 ) register address displaybaseaddress + 80 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4da1 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 4 layer in frame 1. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l4d x ( l4 layer display position x ) register address displaybaseaddress + 84 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4dx r/w r0 rw initial value 0 don?t care this register set s the display start ing position (x coordinate s ) of the l 4 layer on the basis of the origin of the logic frame in pixels .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 174 specifications rev. 1.1 l4dy ( l4 layer display position y ) register address displaybaseaddress + 86 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4dy r/w r0 rw initial va lue 0 don?t care this register sets the display starting position (y coordinates) of the l4 layer on the basis of the origin of the logic frame in pixel s. l4wx ( l4 layer window position x ) register address displaybaseaddress + 154 h bit number 15 14 13 1 2 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4wx r/w r0 rw initial value 0 don?t care this register sets the x coordinates of the display position of the l4 layer window. l4wy ( l4 layer window position y ) register address displaybaseaddress + 156 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4wy r/w r0 rw initial value 0 don?t care this register sets the y coordinates of the display position of the l4 layer window. l4 ww ( l4 layer window width) register address displaybaseaddress + 158 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4 ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l4 layer window. do not specify ?0?. l4 wh ( l4 layer window height) register address displaybaseaddress + 1 5a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display siz e ( height ) of the l4 layer window. setting value + 1 is the height.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 175 specifications rev. 1.1 l5m ( l5 layer mode ) register address displaybaseaddress + 88 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l5c l5flp reserved l5w reserved l5h r/w rw rw r0 rw r0 rw initial value 0 don?t care 0 don?t care bit 11 to 0 l5h ( l5 layer height ) specifies the height of the logic frame of the l5 layer in pixel units. setting value + 1 is the height bit 23 to 16 l5w ( l5 layer memory width ) set s the memory width ( stride ) logic frame of the l5 layer in 64 - byte units bit 30 and 29 l5flp (l5 layer flip mode) set s flipping mode for l5 layer 00 display s frame 0 01 display s frame 1 10 switch es frame 0 and 1 alt ernately for display 11 reserved bit 31 l5c ( l5 layer color mode ) sets the color mode for l5 layer 0 indirect color (8 bits/pixel) mode 1 direct color (16 bits/pixel) mode
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 176 specifications rev. 1.1 l5em ( l5 layer extended mode ) register address displaybaseaddress + 1 60 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 4 3 2 1 0 bit field name l5ec reserved l5om l5wp r/w rw r0 rw rw initial value 00 0 0 bit 0 l5 wp ( l5 layer window position enable ) selects the display position of l5 layer 0 compatibility mode display (br layer supported) 1 window display bit 1 l5om (l5 layer overlay mode) selects the overlay mode for l5 layer 0 compatibility mode 1 extended mode bit 31 to 30 l5ec ( l5 layer extended color mode ) sets extended color mode for l5 layer 00 mode determined by l5c 01 direct color (24 bits/pixel) mode 1x reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 177 specifications rev. 1.1 l5oa0 ( l5 layer origin address 0 ) register address displaybaseaddress + 8c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1 7 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5oa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 5 layer in frame 0 . since lower 4 bits are fixed to ?0?, this addres s is 16 - byte aligned. l5da0 ( l5 layer display address 0 ) register address displaybaseaddress + 90 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5da0 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 5 layer in frame 0. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l5oa1 ( l5 layer origin address 1 ) register address displaybaseaddress + 94 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5oa1 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the origin address of the logic frame of the l 5 layer in fr ame 1 . since lower 4 - bits are fixed to ?0?, this address is 16 - byte aligned. l5oa1 ( l5 layer display address 1 ) register address displaybaseaddress + 98 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bi t field name reserved l5da1 r/w r0 rw initial value 0 don?t care this register sets the origin address of the l 5 layer in frame 1. for the direct color mode (16 bits/pixel) , the lower 1 bit is ?0? and this address is 2 - byte aligned. l5dx ( l5 layer disp lay position x ) register address displaybaseaddress + 9c h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5dx r/w r0 rw initial value 0 don?t care this register set s the display start ing position (x coordinate s ) of the l 5 lay er on the basis of the origin of the logic frame in pixels .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 178 specifications rev. 1.1 l5dy ( l5 layer display position y ) register address displaybaseaddress + 9e h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5dy r/w r0 rw initial value 0 don?t care this register sets the display starting position (y coordinates) of the l5 layer on the basis of the origin of the logic frame in pixel s. l5wx ( l5 layer window position x ) register address displaybaseaddress + 164 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5wx r/w r0 rw initial value 0 don?t care this register sets the x coordinates of the display position of the l5 layer window. l5wy ( l5 layer window position y ) register address displaybaseaddress + 166 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5wy r/w r0 rw initial value 0 don?t care this register sets the y coordinates of the display position of the l5 layer window. l5 ww ( l5 layer window width) register address displaybaseaddr ess + 168 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5 ww r/w r0 rw initial value 0 don?t care this register controls the horizontal direction display size ( width ) of the l5 layer window. do not specify ?0?. l5 wh ( l5 la yer window height) register address displaybaseaddress + 1 6a h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5 wh r/w r0 rw initial value 0 don?t care this register controls the vertical direction display size ( height ) of th e l5 layer window. setting value + 1 is the height.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 179 specifications rev. 1.1 cutc (c u rsor transparent control) register address displaybaseaddress + a0 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cuzt cutc r/w r0 rw rw initial value 0 don?t car e don?t care bit 7 to 0 cutc (cursor transparent code) set s color code handled as transparent code bit 8 cuzt (cursor zero transparency) defines handling of color code 0 0 code 0 as transparency color 1 code 0 as non - transparency color cpm ( cursor priority mode) register address displaybaseaddress + a2 h bit number 7 6 5 4 3 2 1 0 bit field name reserved cen1 cen0 reserved cuo1 cuo0 r/w r0 rw rw r0 rw rw initial value 0 0 0 0 0 0 this register controls the display priority of cursors. c ursor 0 is always preferred to cursor 1. bit 0 cuo0 (cursor overlap 0) sets display priority between cursor 0 and pixels of console layer 0 put s cursor 0 at lower than l0 layer. 1 pu ts cursor 0 at higher than l0 layer. bit 1 cuo1 (cursor overlap 1) sets display priority between cursor 1 and c layer 0 put s cursor 1 at lower than l0 layer. 1 put s cursor 1 at lower than l0 layer. bit 4 cen0 (cursor enable 0) sets enabling display of cursor 0 0 disable d 1 enable d bit 5 cen1 (curso r enable 1) sets enabling display of cursor 1 0 disable d 1 enable d
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 180 specifications rev. 1.1 cuoa0 (cursor - 0 origin address) register address displaybaseaddress + a4 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit fie ld name reserve d cuoa0 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the start address of the cursor 0 pattern. since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. cux0 (cursor - 0 x position) register address display baseaddress + a8 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cux0 r/w r0 rw initial value 0 don?t care this register sets the display position (x coordinates) of the cursor 0 in pixels . the reference position of the coor dinate s is the top left of the cursor pattern. cuy0 (cursor - 0 y position) register address displaybaseaddress + aa h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cuy0 r/w r0 rw initial value 0 don?t care this register sets the display position (y coordinates) of the cursor 0 in pixels . the reference position of the coordinate s is the top left of the cursor pattern.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 181 specifications rev. 1.1 cuoa1 (cursor - 1 origin address) register address displaybaseaddress + ac h bit number 31 30 29 28 27 26 25 2 4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d cuoa1 r/w r0 rw r0 initial value 0 don?t care 0000 this register sets the start address of the cursor 1 pattern. since lower 4 bits are fixed to ?0?, this address is 16 - byte aligned. cux1 (cursor - 1 x position) register address displaybaseaddress + b0 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved cux1 r/w r0 rw initial value 0 don?t care this register sets the display position (x coo rdinates) of the cursor 1 in pixels . the reference position of the coordinate s is the top left of the cursor pattern. cuy1 (cursor - 1 y position) register address displaybaseaddress + b2 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name r eserved cuy1 r/w r0 rw initial value 0 don?t care this register sets the display position (y coordinates) of the cursor 1 in pixels . the reference position of the coordinate s is the top left of the cursor pattern.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 182 specifications rev. 1.1 dls ( display layer select ) register a ddress displaybaseaddress + 180 h bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved dls5 dls4 dls3 dls2 dls1 dsl0 r/w r0 r0 rw r0 rw r0 rw r0 rw r0 rw r0 rw initial value 101 100 0 11 010 001 000 this register defines the blending sequence. bit 3 to 0 dsl0 ( display layer select 0 ) selects the top layer subjected to blending. 0000 l0 layer 0001 l1 layer : : 0101 l5 layer 0110 reserved : : 0110 reserved 0111 not selected bit 7 to 4 dsl1 ( display layer select 1 ) selects the second layer subjected to blending. the bit values are the same as dsl0. bit 11 to 8 dsl2 ( display layer select 2 ) selects the third layer subjected to blending. the bit values are the same as dsl0. bit 15 to 12 dsl3 ( display layer select 3 ) selects the fourth layer subjected to blending. the bit values are the same as dsl0. bit 19 to 16 dsl4 ( display layer select 4 ) selects the fifth layer subjected to blending. t he bit values are the same as dsl0. bit 23 to 20 dsl5 ( display layer select 5 ) selects the bottom layer subjected to blending. the bit values are the same as dsl0.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 183 specifications rev. 1.1 dbgc ( display background color ) register address displaybaseaddress + 184 h bit n umber 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved dbgr dbgg dbgb r/w r0 initial value this register specifies the color to be displayed in areas outside the display area of each laye r on the window. bit 7 to 0 dbgb ( display background blue ) specifies the blue level of the background color. bit 15 to 8 dbgg ( display background green ) specifies the green level of the background color. bit 23 to 16 dbgr ( display background r ed ) specifies the red level of the background color.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 184 specifications rev. 1.1 l0bld ( l0 blend ) register address displaybaseaddress + b4 h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l0be l0bs l0bi l0bp reserved l 0br r/w r0 rw rw rw rw r0 rw initial value 0 0 0 0 0 this register specifies the blend parameters for the l0 layer. this register corresponds to bratio or bmode for previous products. bit 7 to 0 l0br ( l0 layer blend ratio ) sets the blend ratio. b asically, the blend ratio is setting value/256. bit 13 l0bp (l0 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l0br used as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l0bi (l0 layer blend increme nt) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l0bs ( l0 layer blend select ) selects the blend calculation expression. 0 upper image blend r atio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l0be (l0 layer blend enable) this bit enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the ble nd mode must be specified using l0be, and alpha must also be enabled for l0 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 185 specifications rev. 1.1 l1bld ( l1 blend ) register ad dress displaybaseaddress + 188 h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l1be l1bs l1bi l1bp reserved l1br r/w r0 rw rw rw rw r0 rw initial value 0 0 0 0 0 this register specifies the blend parameters for the l1 layer. bit 7 to 0 l1br ( l1 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l1bp (l1 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l1br used as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l1bi (l1 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l1bs ( l1 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l1be (l1 layer blend enable) this bit enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l1be, and alpha must also be enabled for l1 layer display data. for direct color, alpha is specified using the msb of dat a; for indirect color, alpha is specified using the msb of palette data.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 186 specifications rev. 1.1 l2bld ( l2 blend ) register address displaybaseaddress + 18c h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l2be l2bs l2b i l2bp reserved l2br r/w r0 rw rw rw rw r0 rw initial value 0 0 0 0 0 this register specifies the blend parameters for the l2 layer. bit 7 to 0 l2br ( l2 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l2bp (l2 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l2br used as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l2bi (l2 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l2bs ( l2 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper ima ge (1 ? blend ratio) + lower image blend ratio bit 16 l2be (l2 layer blend enable) this bit enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l2be, and alpha must also be enabled for l2 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 187 specifications rev. 1.1 l3bld ( l3 blend ) register address displaybaseaddress + 190 h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l3be l3bs l3bi l3bp reserved l3br r/w rw rw rw rw rw initial value 0 0 0 0 0 this register specifies the blend parameters for the l3 layer. bit 7 to 0 l3br ( l 3 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l3bp (l3 layer blend plane ) specifies that the l5 layer is the blend plane. 0 value of l3br used as blend ratio 1 pixel of l5 layer used as blen d ratio bit 14 l3bi (l3 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l3bs ( l3 layer blend select ) selects the blend ca lculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l3be (l3 layer blend enable) this bit enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l3be, and alpha must also be enabled for l3 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 188 specifications rev. 1.1 l4bld ( l4 blend ) register address displaybaseaddress + 194 h bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l4be l4bs l4bi l4bp reserved l4br r/w r0 rw rw rw rw r0 rw initia l value 0 0 0 0 0 this register specifies the blend parameters for the l4 layer. bit 7 to 0 l4br ( l4 layer blend ratio ) sets the blend ratio. basically, the blend ratio is setting value/256. bit 13 l4bp (l4 layer blend plane ) specifies that th e l5 layer is the blend plane. 0 value of l4br used as blend ratio 1 pixel of l5 layer used as blend ratio bit 14 l4bi (l4 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l4bs ( l4 layer blend select ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l4be (l4 layer blend enable) this bit enables blending. 0 overlay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l4be, and alpha must also be enabled for l4 layer display data. for direc t color, alpha is specified using the msb of data; for indirect color, alpha is specified using the msb of palette data.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 189 specifications rev. 1.1 l5bld ( l5 blend ) register address displaybaseaddress + 198h bit number 31 30 29 28 ----- 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserved l5be l5bs l5bi reserved l5br r/w r0 rw rw rw r0 rw initial value 0 0 0 this register specifies the blend parameters for the l5 layer. bit 7 to 0 l5br ( l5 layer blend ratio ) sets the blend ratio. basically, t he blend ratio is setting value/256. bit 14 l5bi (l5 layer blend increment) selects whether or not 1/256 is added when the blend ratio is not ? 0 ? . 0 blend ratio calculated as is 1 1/256 added when blend ratio 1 0 bit 15 l5bs ( l5 layer blend s elect ) selects the blend calculation expression. 0 upper image blend ratio + lower image (1 ? blend ratio) 1 upper image (1 ? blend ratio) + lower image blend ratio bit 16 l5be (l5 layer blend enable) this bit enables blending. 0 over lay via transparent color 1 overlay via blending before blending, the blend mode must be specified using l5be, and alpha must also be enabled for l5 layer display data. for direct color, alpha is specified using the msb of data; for indirect color, alp ha is specified using the msb of palette data.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 190 specifications rev. 1.1 l0tc ( l0 layer transparency control) register address displaybaseaddress + bc h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l0zt l0tc r/w rw rw initial value 0 0 this register sets the transparent color for the l0 layer. color set by this register is transparent in blend mode. when l0tc = 0 and l0zt = 0, color 0 is displayed in black (transparent). this register corresponds to the ctc register for previous products. bit 14 to 0 l0tc ( l0 layer transparent color ) set s transparent color code for the l0 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 15 l0zt ( l0 layer zero transparency ) sets handling of color code 0 in l0 layer 0: code 0 as transparency c olor 1: code 0 as non - transparency color l2tc ( l2 layer transparency control ) register address displaybaseaddress + c2 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l2zt l2tc r/w rw rw initial value 0 0 this register sets the tr ansparent color for the l2 layer. when l2tc = 0 and l2zt = 0, color 0 is displayed in black (transparent). this register corresponds to the mltc register for previous products. bit 14 to 0 l2tc (l2 layer transparent color) set s transparent color code fo r the l2 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 15 l2zt (l2 layer zero transparency) sets handling of color code 0 in l2 layer 0 code 0 as transparency color 1 code 0 as non - transparency color
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 191 specifications rev. 1.1 l3tc ( l3 layer tr ansparency control ) register address displaybaseaddress + c0 h bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l3zt l3tc r/w rw rw initial value 0 0 this register sets the transparent color for the l3 layer. when l3tc = 0 and l3zt = 0, color 0 is displayed in black (transparent). this register corresponds to the mltc register for previous products. bit 14 to 0 l3tc (l3 layer transparent color) set s transparent color code for the l3 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 15 l3zt (l3 layer zero transparency) sets handling of color code 0 in l3 layer 0 code 0 as transparency color 1 code 0 as non - transparency color l0e tc ( l0 layer extend transparency control) register address displaybaseaddre ss + 1a0 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l0etz reserved l0tec r/w rw r0 rw initial value 0 0 this register sets the transparent color for the l0 layer. the 24 bits/pixel tra nsparent color is set using this register. the lower 15 bits of this register are physically the same as l0tc. also, l0etz is physically the same as l0tz. when l0etc = 0 and l0ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l0etc (l0 la yer extend transparent color) set s transparent color code for the l0 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l0ezt (l0 layer extend zero transparency) sets handling of color code 0 in l0 layer 0 code 0 as transp arency color 1 code 0 as non - transparency color
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 192 specifications rev. 1.1 l1etc ( l1 layer extend transparency control ) register address displaybaseaddress + 1a4 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l1etz reserved l1tec r/w rw r0 rw initial value 0 0 this register sets the transparent color for the l1 layer. when l1etc = 0 and l1ezt = 0, color 0 is displayed in black (transparent). for ycbcr display, transparent color checking is not performed; proces sing is always performed assuming that transparent color is not used. bit 23 to 0 l1etc (l1 layer extend transparent color) set s transparent color code for the l1 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l1ezt (l1 l ayer extend zero transparency) sets handling of color code 0 in l1 layer 0 code 0 as transparency color 1 code 0 as non - transparency color l2etc ( l2 layer extend transparency control ) register address displaybaseaddress + 1a8 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l2etz reserved l2tec r/w rw r0 rw initial value 0 0 this register sets the transparent color for the l2 layer. the 24 bits/pixel transparent color is set using th is register. the lower 15 bits of this register are physically the same as l2tc. also, l2etz is physically the same as l2tz. when l2etc = 0 and l2ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l2etc (l2 layer extend transparent color) set s transparent color code for the l2 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l2ezt (l2 layer extend zero transparency) sets handling of color code 0 in l2 layer 0 code 0 as transparency color 1 code 0 as non - transparency color
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 193 specifications rev. 1.1 l3etc ( l3 layer extend transparency control ) register address displaybaseaddress + 1ac h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l3etz reserved l3tec r/w rw r0 rw initial value 0 0 this register sets the transparent color for the l3 layer. the 24 bits/pixel transparent color is set using this register. the lower 15 bits of this register are physically the same as l3tc. also, l3etz is physically the same as l3tz . when l3etc = 0 and l3ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l3etc (l3 layer extend transparent color) set s transparent color code for the l3 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l3ez t (l3 layer extend zero transparency) sets handling of color code 0 in l3 layer 0 code 0 as transparency color 1 code 0 as non - transparency color l4etc ( l4 layer extend transparency control ) register address displaybaseaddress + 1b0 h bit number 3 1 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l4etz reserved l4tec r/w rw r0 rw initial value 0 0 this register sets the transparent color for the l4 layer. this register sets the transparent color for the l4 layer. when l4etc = 0 and l4ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l4etc (l4 layer extend transparent color) set s transparent color code for the l4 layer. in indirect color mode (8 bits/pixel) bits 7 to 0 are used. bit 31 l4ezt (l4 layer extend zero transparency) sets handling of color code 0 in l4 layer 0 code 0 as transparency color 1 code 0 as non - transparency color
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 194 specifications rev. 1.1 l5etc ( l5 layer extend transparency control ) register address displaybaseaddress + 1b4 h bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name l5etz reserved l5tec r/w rw r0 rw initial value 0 0 this register sets the transparent color for the l5 layer. this register sets the transp arent color for the l5 layer. when l5etc = 0 and l5ezt = 0, color 0 is displayed in black (transparent). bit 23 to 0 l5etc (l5 layer extend transparent color) set s transparent color code for the l5 layer. in indirect color mode (8 bits/pixel) bits 7 t o 0 are used. bit 31 l5ezt (l5 layer extend zero transparency) sets handling of color code 0 in l5 layer 0 code 0 as transparency color 1 code 0 as non - transparency color
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 195 specifications rev. 1.1 l0 pal0 - 255 ( l0 layer palette 0 - 255) register address displaybaseaddress + 400 h -- displaybaseaddress + 7ff h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r g b r/w rw r0 rw r0 rw r0 rw r0 initial value don?t care 0000000 don?t care 00 don?t care 00 don?t care 00 these are color palette registers for l0 layer and cursors. in the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of tha t pixel. this register corresponds to the cpaln register for previous products. bit 7 to 2 b (blue) set s blue color component bit 15 to 10 g (green) set s green color component bit 23 to 18 r (red) set s red color component bit 31 a (alph a) specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 blending not performed even when blending mode enabled overlay is performed via transparent color. 1 blending performed
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 196 specifications rev. 1.1 l1 pal0 - 255 ( l1 layer pal ette 0 - 255) register address displaybaseaddress + 8 00 h -- displaybaseaddress + b ff h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r g b r/w rw r0 rw r0 rw r0 rw r0 initial value don?t care 0000000 don?t care 00 don?t care 00 don?t care 00 these are color palette registers for l1 layer and cursors. in the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. this register corresponds to the mbpaln register for previous products. bit 7 to 2 b (blue) set s blue color component bit 15 to 10 g (green) set s green color component bit 23 to 18 r (r ed) set s red color component bit 31 a (alpha) specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 blending not performed even when blending mode enabled overlay is performed via transparent color. 1 blending performed
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 197 specifications rev. 1.1 l2 pal0 - 255 ( l2 layer palette 0 - 255) register address displaybaseaddress + 10 00 h -- displaybaseaddress + 13 ff h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r g b r/w rw r0 rw r0 rw r0 rw r0 initial value don?t care 0000000 don?t care 00 don?t care 00 don?t care 00 these are color palette registers for l2 layer and cursors. in the indirect color mode, a color code in the display frame indicates the palette reg ister number, and the color information set in that register is applied as the display color of that pixel. bit 7 to 2 b (blue) set s blue color component bit 15 to 10 g (green) set s green color component bit 23 to 18 r (red) set s red color c omponent bit 31 a (alpha) specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 blending not performed even when blending mode enabled overlay is performed via transparent color. 1 blending performed
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 198 specifications rev. 1.1 l3 pal0 - 255 ( l3 layer palette 0 - 255) register address displaybaseaddress + 1 400 h -- displaybaseaddress + 1 7ff h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r g b r/w rw r0 rw r0 rw r0 rw r0 initial value don?t care 0000000 don?t care 00 don?t care 00 don?t care 00 these are color palette registers for l3 layer and cursors. in the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. bit 7 to 2 b (blue) set s blue color component bit 15 to 10 g (green) set s green color component bit 23 to 18 r (red) set s red color component bit 31 a (alpha) specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 blending not performed even when blending mode enabled overlay is performed via transparent color. 1 blending performed
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 199 specifications rev. 1.1 10.2.4 draw ing c ontrol r eg isters ctr (control register) register address drawbaseaddress + 400 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fo ce fcnt nf ff fe ss ds ps r/w rw rw rw r r r r r r r ini tial value 0 0 0 011101 0 0 1 00 00 00 this register indicates draw ing flags and status information . bits 24 to 22 are not cleared until 0 is set. bit 1 and 0 ps (pixel engine status) indicate status of pixel engine unit 00 idle 01 busy 10 reserved 11 reserved bit 5 and 4 ds (dda status) indicate status of dda 00 idle 01 busy 10 busy 11 reserved bit 9 and 8 ss (setup status) indicate status of setup unit 00 idle 01 busy 10 reserved 11 reserved bit 12 fe (fi fo empty) indicates whether data contained or not in display list fifo 0 valid data 1 no valid data bit 13 ff (fifo full) indicates whether display list fifo is full or not 0 not full 1 full bit 14 nf (fifo near full) indicates how e mpty the display list fifo is 0 empty entries equal to or more than half
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 200 specifications rev. 1.1 1 empty entries less than half bit 20 to 15 fcnt (fifo counter) indicate s count of empty entries of display list fifo (0 to 100000 b ) bit 23 - 22 ce (display list command e rror) indicates command error occurrence 0 0 normal 1 1 command error detected bit 24 fo (fifo overflow) indicates fifo overflow occurrence 0 normal 1 fifo overflow detected
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 201 specifications rev. 1.1 ifsr (input fifo status register) register address drawbaseaddres s + 404 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name nf ff fe r/w r r r initial value 0 0 1 this is a mirror register for bits 14 to 12 of the ctr register. ifcnt (input fifo count er) register address drawbaseaddress + 408 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fcnt r/w r initial value 011101 this is a mirror register for bits 19 to 15 of the ctr regi ster. sst (setup engine status) register address drawbaseaddress + 40c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ss r/w r initial value 00 this is a miller register for bits 9 to 8 of the ctr register. dst (dda status) register address drawbaseaddress + 410 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ds r/w rw initial value 00 this is a mirror register for bits 5 to 4 of the ctr register. pst (pixel engine status) register address drawbaseaddress + 414 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ps r/w r initial value 00 this is a mirror register for bits 1 to 0 of the ctr register. est (error status) register address drawbaseaddress + 418 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fo pe ce r/w rw rw rw initial value 0 0 0 this is a mirror register for bits 24 to 22 of the ctr register.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 202 specifications rev. 1.1 10.2.5 draw ing mode r egisters when wr i te to the registers, use the setregister command. the registers cannot be accessed from the cpu. mdr0 (mode register for miscellaneous ) register address drawbaseaddress + 420 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name zp cf cy cx bsv bsh r/w rw rw rw rw rw rw initial value 0 00 0 0 00 00 bit 1 to 0 bs h (bitmap scale horizontal) set s horizontal zoom ratio of bitmap draw 00 x1 01 x2 10 x1/2 01 reserved bit 3 to 2 bsv (bitmap scale vertical) set s vertical zoom ratio of bitmap draw 00 x1 01 x2 10 x1/2 01 reserved bit 8 cx (clip x enable) sets x coordinate s clipping mode 0 disable d 1 enable d bit 9 cy (clip y enable) sets y coordinate s clipping mode 0 disable d 1 enable d bit 16 and 15 cf (color format) sets drawing color format 0 0 indirect color mode (8 bits /pixel) 0 1 direct color mode (16 bits/pixel) 10 direct color mode (24 bits/pixel) bit 20 zp ( z precision) sets the precision of the z value used for erasing hidden planes. 16 bits/pixel 8 bits/pixel
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 203 specifications rev. 1.1 mdr1 /mdr1s/mdr1b (mode register for lin e /for shadow/for border ) register address drawbaseaddress + 424 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name lw bp bl log bm zw zcl zc r/w rw rw rw rw rw rw rw rw initial val ue 00000 0 0 0011 0 0 0000 0 this register sets the mode of line and pixel drawing . this register is used for the body primitive, for the shade primitive, for the edge primitive. the value after a drawing that involves the shade primitive, the edge p rimitive is the value set for mdr1. please set zc bit ( bit 2) to 0 when draw bltcopyaltalphablendp command. bit 1 as (alpha shading mode) sets the shading mode for alpha. 0 alpha flat shading 1 alpha gouraud shading bit 2 zc (z compare mode) sets z comparison mode 0 disable d 1 enable d bit 5 to 3 zcl (z compare logic) select s type of z comparison 000 never 001 always 010 less 011 lequal 100 equal 101 gequal 110 greater 111 notequal bit 6 zw (z write mode ) sets z write mode 0 writes z values. 1 not write z values. bit 8 to 7 bm (blend mode) set s blend mode 00 normal (source copy) 01 alpha blending 10 drawing with logic operation 11 reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 204 specifications rev. 1.1 bit 12 to 9 log (logical operation) set s type of lo gic operation 0000 clear 0001 and 0010 and reverse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 equiv 1010 invert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set bit 19 bl (b roken line) selects line type 0 solid line 1 broken line bit 20 bp (broken line period) selects broken line cycle 0: 32 bits 1: 24 bits bit 28 to 24 lw (line width) set s line width for drawing line 00000 1 pixel 00001 2 pixels : : 11111 32 pixels
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 205 specifications rev. 1.1 mdr 2/mdr2s/mdr2tl (mode register for polygon/for shadow/for topleft ) register address drawbaseaddress + 428 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tt log bm zw zcl zc as sm r/w rw rw rw rw rw rw rw rw initial value 00 0011 0 0 0000 0 0 0 this register sets the polygon draw ing mode. this register is used for the body primitive, for the shade primitive, and for the top - left non - applicable primitiv e. the value after a drawing that involves the shade primitive or the top - left non - applicable primitive is the value set for mdr2. mdr2s register is able to use only sm=0, as=0 and tt=00 settings. bit 0 sm (shading mode) sets shading mode 0 flat shadi ng 1 gouraud shading bit 1 as (alpha shading mode) sets alpha shading mode . this mode is enabled for only alpha. 0 alpha flat shading 1 alpha gouraud shading bit 2 zc (z compare mode) sets z comparison mode 0 disable d 1 enable d b it 5 to 3 zcl (z compare logic) select s type of z comparison 000 never 001 always 010 less 011 lequal 100 equal 101 gequal 110 greater 111 notequal bit 6 zw (z write mask) sets z write mode 0 writes z values 1 not write z values
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 206 specifications rev. 1.1 bit 8 to 7 bm (blend mode) set s blend mode 00 normal (source copy) 01 alpha blending 10 drawing with logic operation 11 reserved bit 12 to 9 log (logical operation) set s type of logic operation 0000 clear 0001 and 0010 and rev erse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 equiv 1010 invert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set bit 29 to 28 tt (texture - tile select) select s texture or tile pattern 00 neither used 01 enable d tiling 10 enable d texture 11 reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 207 specifications rev. 1.1 mdr3 (mode register for texture) register address d rawbaseaddress + 42c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name ba tab tbl tws twt tf tc r/w rw rw rw rw rw rw rw initial value 0 00 00 00 00 0 0 this register sets the texture mapping mode. bit 3 tc (texture coordinates correct) sets texture coordinates correction mode 0 disable d 1 enable d bit 5 tf (texture filtering) sets type of texture interpolation ( filtering) 0 point sampling 1 bi - linear filtering bit 9 and 8 twt (texture wrap t) set s type of texture coordinate s t direction wrapping 00 repeat 01 cramp 10 border 11 reserved bit 11 and 10 tws (texture wrap s) set s type of texture coordinate s s direction wrapping 00 repeat 01 cramp 10 border 11 reserved bit 17 and 16 tbl (texture blend mode) set s texture blending mode 00 de - curl 01 modulate 10 stencil 11 reserved bit 21 and 20 tab (texture alpha blend mode) sets texture blending mode the stencil mode and the stencil alpha mode are enabled only when the mdr2 register blend mode (bm) is set to the alpha blending mod e. if it is not set to the alpha blending mode, the stencil mode and stencil alpha mode perform the same function as the normal mode.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 208 specifications rev. 1.1 00 normal 01 stencil 10 stencil alpha 11 reserved bit 24 ba (bilinear accelerate mode) improve s the perfor mance of bi - linear filtering, although a texture area of four times the default texture area is used. 0 default texture area used 1 texture area four times default texture area used
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 209 specifications rev. 1.1 mdr4 (mode register for blt) register address drawbaseaddress + 43 0 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name log bm te r/w rw rw rw initial value 0011 00 0 this register controls the blt mode. bit 1 te (transparent enable) sets trans parent mode 0: not perform transparent processing 1: not draw pixels that corresponds to set transparent color in blt ( transparancy copy) note: set the blend mode (bm) to normal. bit 8 to 7 bm (blend mode) set s blend mode 00 normal (source cop y) 01 reserved 10 drawing with logic operation 11 reserved bit 12 to 9 log (logical operation) set s logic operation 0000 clear 0001 and 0010 and reverse 0011 copy 0100 and inverted 0101 nop 0110 xor 0111 or 1000 nor 1001 equ iv 1010 invert 1011 or reverse 1100 copy inverted 1101 or inverted 1110 nand 1111 set
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 210 specifications rev. 1.1 mdr 7 (mode register for extension ) register address drawbaseaddress + 43 c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name lth ez gg pgh pth pzh r/w w w w w w w initial value 1 0 0 0 0 0 this register controls the blt mode. bit 0 pzh ( polygon z hard mask ) sets polygon - fill z reference mode 0: hard mask on ( compatible orchid) 1: hard mask off ( extension mode) bit 1 pth ( polygon texture hard mask ) set s polygon - texture mode 0 : hard mask on ( compatible orchid) 1 : hard mask off ( extension mode) bit 2 pgh ( polygon gouraud shading hard mask ) set s polygon - gouraud sh ading mode 0 : hard mask on ( compatible orchid) 1 : hard mask off ( extension mode) bit 4 gg ( gray scale gouraud shading ) set s gray scale gouraud shading mode 0 : hard mask on ( compatible orchid) 1 : hard mask off ( extension mode) bit 5 ez ( extend z ) set s new z mode 0 : z 1 bit extend off ( compatible orchid) 1 : z 1 bit extend on ( extension mode) bit 6 lth ( line texture hard mask ) set s line texture mode 0 : hard mask on ( compatible orchid) 1 : hard mask off ( extension mod e) note: this register is used for gray scale gouraud shading. this register is changed by internal processing . please don ? t set these bits except gg bit. in case of gray scale gouraud shading drawing, please set this register to the follows. 1. set this r egister to 0x00000050( gg bit and lth bit equal to 1) before drawing. 2. set this register to 0x00000040( lth bit equal to 1) after drawing.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 211 specifications rev. 1.1 fbr (frame buffer base) register address drawbaseaddress + 440 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fbase r/w rw r0 initial value don?t care 0 this register stores the base address of the drawing frame. xres (x resolution) register address drawbaseaddress + 444 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name xres r/w rw initial value don?t care this register sets the drawing frame horizontal resolution. zbr (z buffer base) register address drawbaseaddress + 448 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name zbase r/w rw r0 initial value don?t care 0 this register sets the z buffer base address. tbr (texture memory base) register address draw baseaddress + 44c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tbase r/w rw r0 initial value don?t care 0 this register sets the texture memory base address. pfbr (2d polygon flag - buffer base) register address drawbaseaddress + 450 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name pfbase r/w rw r0 initial value don?t care 0 this register sets the polygon flag bu ffer base address.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 212 specifications rev. 1.1 cxmin (clip x minimum) register address drawbaseaddress + 454 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name clipxmin r/w rw initial value don?t care this regist er sets the clip frame minimum x position. cxmax (clip x maximum) register address drawbaseaddress + 458 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name clipxmax r/w rw initial value don?t care this register sets the clip frame maximum x position. cymin (clip y minimum) register address drawbaseaddress + 45c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name clipymin r /w rw initial value don?t care this register sets the clip frame minimum y position. cymax (clip y maximum) register address drawbaseaddress + 460 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name clipymax r/w rw initial value don?t care this register sets the clip frame maximum y position.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 213 specifications rev. 1.1 txs (texture size) register address drawbaseaddress + 464 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name txsn txsm r/w rw rw initial value 000010000000 000010000000 this register specifies the texture size (m, n). bit 12 to 0 txsm (texture size m) set s horizontal texture size. any power of 2 between 4 and 4096 can be used. values that are not a power of 2 cannot be used. 0_0000_0000_0100 m=4 0_0010_0000_0000 m=512 0_0000_0000_1000 m=8 0_0100_0000_0000 m=1024 0_0000_0001_0000 m=16 0_1000_0000_0000 m=2048 0_0000_0010_0000 m=32 1_0000_0000_0000 m=4096 0_0000_0 100_0000 m=64 0_0000_1000_0000 m=128 0_0001_0000_0000 m=256 other than the above setting disabled bit 28 to 16 txsn (texture size n) set s vertical texture size. any power of 2 between 4 and 4096 can be used. values that are not a power of 2 cannot be used. 0_0000_0000_0100 n =4 0_0010_0000_0000 n =512 0_0000_0000_1000 n =8 0_0100_0000_0000 n =1024 0_0000_0001_0000 n =16 0_1000_0000_0000 n =2048 0_0000_0010_0000 n =32 1_0000_0000_0000 n =4096 0_0000_0100_0000 n =64 0_0000_1000_0000 n =128 0_0001_0000_0000 n =256 other than the above setting disabled
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 214 specifications rev. 1.1 tis (tile size) register address drawbaseaddress + 468 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tisn tism r/w rw rw initial value 1000000 1000000 this register specifies the tile size (m, n). bit 6 to 0 tism (title size m) set s horizontal tile size. any power of 2 between 4 and 64 can be used. values that are not a power of 2 cannot be used. 0.000100 m=4 0001000 m=8 0010000 m=16 0100000 m=32 1000000 m=64 other than the above setting disabled bit 22 to 16 tisn (title size n) set s vertical tile size. any power of 2 between 4 and 64 can be used. values that are not a power of 2 cannot be used. 0000100 n=4 0001000 n=8 0010000 n=16 0100000 n=32 1000000 n=64 other than the above setting disabled toa (t iling offset address) register address drawbaseaddress + 46c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name xbo r/w rw initial value don?t care this register sets the texture buffer offset address. using this offset value, texture patterns can be referred to the texture buffer memory. toa is used for only t he tiling drawing, and is not used for referring the texture pattern. specify the word - aligned byte address (16 bits). (bit 0 is always ?0?.)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 215 specifications rev. 1.1 sho (shadow offset) register address drawbaseaddress + 470 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 1 8 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name shoffs r/w rw initial value don?t care this register sets the offset address of the shadow relative to the body primitive at drawing with shadow. at body drawing, this offset address is se t to ? 0 ? ; at shadow drawing, the offset address calculated from each offset value of the x coordinates and of the y coordinates is set. this register is hardware controlled. abr (alpha map base) register address drawbaseaddress + 474 h bit number 31 30 2 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name abase r/w rw r0 initial value don?t care 0 this register sets the base address of the alpha map.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 216 specifications rev. 1.1 fc (foreground color) register address drawbaseaddress + 480 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fgc 8/16 r/w rw initial value 0 this register sets the drawing foreground color. this color is for the object color for flat shadi ng and foreground color for bitmap draw ing and broken line draw ing. all bits set to ?1? are drawn in the color set at this register. 8 bit color mode: bit 7 to 0 fgc8 (foreground 8 bit color) sets the indirect color for the foreground (color index code ). bit 31 to 8 these bits are not used. 16 bit color mode: bit 15 to 0 fgc16 (foreground 16 bit color) this field sets the 16 - bit direct color for the foreground. note that the handling of bit 15 is different from that in orchid. up to orchid, bit 15 is ? 0 ? for other than bit map and rectangular drawing, but starting with coral, the setting value is reflected in memory as is. this bit is also reflected in bit 15 of the 16 - bit color at gouraud shading. bit 31 to 16 these bits are not used.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 217 specifications rev. 1.1 bc (bac kground color) register address drawbaseaddress + 484 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name bgc8/16 r/w rw initial value 0 this register sets the drawing frame background co lor. this color is used for the background color of bitmap draw ing and broken line draw ing . at bitmap drawing, all bits set to ? 0 ? are drawn in the color set at this register. bt bit of this register allows the background color of be transparent (no draw ing). 8 bit color mode: bit 7 to 0 bgc8 (background 8 bit color) sets the indirect color for the background (color index code) bit 14 to 8 not used bit 15 bt (background transparency) sets the transparent mode for the background color 0 background drawn using color set for bgc field 1 background not drawn (transparent) bit 31 to 16 not used 16 bit color mode: bit 14 to 0 bgc16 (background 16 bit color) sets 16 - bit direct color (rgb) for the background bit 15 bt (background transparency) s ets the transparent mode for the background color 0 background drawn using color set for bgc field 1 background not drawn (transparent) bit 31 to 16 not used
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 218 specifications rev. 1.1 alf (alpha factor) register address drawbaseaddress + 488 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name a r/w rw initial value 0 this register sets the alpha blending coefficient . blp (broken line pattern) register address drawbaseaddress + 48c h bit number 31 30 29 2 8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name blp r/w rw initial value 0 this register sets the broken - line pattern. the bit 1 set in the broken - line pattern is drawn in the foreground color and bit 0 is dr awn in the background color. the line pattern for 1 pixel line is laid out in the direction of msb to lsb and when it reaches lsb, it goes back to msb . the blpo register manage s the bit numbers of the broken - line pattern. 32 or 24 bits can be selected a s the repetition of the broken - line pattern by the bp bit of the mdr1 register. when 24 bits are selected, bits 23 to 0 of the blp register are used. tbc (texture border color) register address drawbaseaddress + 494 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name bc8/16 r/w rw initial value 0 this register sets the border color for texture mapping. 8 bit color mode: bit 7 to 0 bc8 (border color) sets the 8 - bit direct color for the te xture border color 16 bit color mode: bit 15 to 0 bc16 (border color) sets the 16 - bit direct color for the texture border color blpo (broken line pattern offset) register address drawbaseaddress + 3e0 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name bcr r/w rw initial value 11111 this register stores the bit number of the broken - line pattern set to blp registers, for broken line drawing. this value is decremented at each pixel d raw ing . broken line can be drawn starting from any starting position of the specified broken - line pattern by setting any value at this register. when no write is performed, the position of broken - line pattern is sustained.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 219 specifications rev. 1.1 pnbpi (pixel number of broken line pattern pointer inter lock) register address drawbaseaddress + 28c h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name pn r/w w initial value 00000 this register is valid when bc( 16bit)=1 of the gmdr1e register, and determines how many pixels should be fixed before and behind reference address of broken - line pattern(broken - line pointer). the recommended value is same as the line width.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 220 specifications rev. 1.1 10.2.6 triangle draw ing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or using the setregister command. (xy coordinate s register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ys 0000 h s s s s int frac xs 0004 h s s s s int frac dxdy 0008 h s s s s int frac xus 000c h s s s s int frac dxudy 0010 h s s s s int frac xls 0014 h s s s s int frac dxldy 0018 h s s s s int frac usn 001 c h 0 0 0 0 int 0 lsn 0020 h 0 0 0 0 i nt 0 address offset value from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets (x, y) coordinates for triangle drawing ys y coordinate s s tart position of long edge xs x coordinate s start position of long edge corresponding to ys dxdy x dda value of long edge direction xus x coordinate s start position of upper edge dxudy x dda value of upper edge direction xls x coordinate s start positi on of lower edge dxldy x dda value of lower edge direction usn count of spans of upper triangle. if this value is ?0?, the upper triangle is not drawn. lsn count of spans of lower triangle. if this value is ?0?, the lower triangle is not drawn.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 221 specifications rev. 1.1 (co lor setting register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rs 0040 h 0 0 0 0 0 0 0 0 int frac drdx 0044 h s s s s s s s s int frac drdy 0048 h s s s s s s s s int frac gs 004c h 0 0 0 0 0 0 0 0 int frac dgdx 0050 h s s s s s s s s int frac dgdy 0054 h s s s s s s s s int frac bs 0058 h 0 0 0 0 0 0 0 0 int frac dbdx 005c h s s s s s s s s int frac dbdy 0060 h s s s s s s s s int frac address offset from drawbaseaddress s sign bit or sign ext ension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets color parameters for triangle drawing. these parameters are enabled in the gouraud shading mode. rs r value at (xs, ys, zs) of lo ng edge corresponding to ys drdx r dda value of horizontal direction drdy r dda value of long edge gs g value at (xs, ys, zs) of long edge corresponding to ys dgdx g dda value of horizontal direction dgdy g dda value of long edge bs b value at (xs, y s, zs) of long edge corresponding to ys dbdx b dda value of horizontal direction dbdy b dda value of long edge (z coordinate s register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 zs 0080h 0 in t frac dzdx 0084h s int frac dzdy 008 8 h s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets z coordinate s for 3d triangle drawing zs z coordinate start position of long edge dzdx z dda value of horizontal direction dzdy z dda value of long edge
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 222 specifications rev. 1.1 (texture coordinate s - setting register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1 2 11 10 9 8 7 6 5 4 3 2 1 0 ss 00c0 h s s s int frac dsdx 00c4 h s s s int frac dsdy 00c8 h s s s int frac ts 00cc h s s s int frac dtdx 00d0 h s s s int frac dtdy 00d4 h s s s int frac qs 00d8 h 0 0 0 0 0 0 0 int frac dqdx 00dc h s s s s s s s int frac d qdy 00e0 h s s s s s s s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets texture coordinate s parameters for tr iangle drawing ss s texture coordinate s (xs, ys, zs) of long edge corresponding to ys dsdx s dda value of horizontal direction dsdy s dda value of long edge direction ts t texture coordinate s (xs, ys, zs) of long edge corresponding to ys dtdx t dda va lue of horizontal direction dtdy t dda value of long edge direction qs q (perspective correction value) of texture at (xs, ys, zs) of long edge corresponding to ys dqdx q dda value of horizontal direction dqdy q dda value of long edge direction
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 223 specifications rev. 1.1 10.2.7 line draw ing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or by using the setregister command. (coordinate s setting register) register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1 2 11 10 9 8 7 6 5 4 3 2 1 0 lpn 0140 h 0 0 0 0 int 0 lxs 0144 h s s s s int frac lxde 0148 h s s s s s s s s s s s s s s s int frac lys 014c h s s s s int frac lyde 0150 h s s s s s s s s s s s s s s s int frac lzs 0154 h s int frac lzde 0158 h s int frac address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate s parameters for line drawing lpn pixel count of principal a xis direction lxs x coordinate s start position of draw line (in principal axis x ) integer value of x coordinate s rounded off (in principal axis y) x coordinate s in form of fixed point data lxde inclination data for x coordinate s (in principal axis x) inc rement or decrement according to drawing direction (in principal axis y) fraction part of dx/dy lys y coordinate s start position of draw line (in principal axis x) y coordinate s in form of fixed point data (in principal axis y) integer value of y coordina te s rounded off lyde inclination data for y coordinate s (in principal axis x) fraction part of d y/ d x (in principal axis y) increment or decrement according to drawing direction lzs z coordinate s start position of line draw ing line lzde z inclination
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 224 specifications rev. 1.1 10.2.8 pixel drawing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or using the setregister command. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pxdc 0180 h 0 0 0 0 int 0 pydc 0184 h 0 0 0 0 int 0 pzdc 0188 h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point dat a sets coordinate s parameter for drawing pixel . the foreground color is used. pxdc set s x coordinate s position pydc set s y coordinate s position pzdc set s z coordinate s position 10.2.9 rectangle draw ing registers each register is used by the drawing commands . the registers cannot be accessed from the cpu or using the setregister command . register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxs 0200 h 0 0 0 0 int 0 rys 0204 h 0 0 0 0 int 0 rsizex 0208 h 0 0 0 0 int 0 rsizey 020c h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate s parameters for rectan gle drawing. the foreground color is used. rxs set s the x coordinate s of top left vertex rys set s the y coordinate s of top left vertex rsizex set s horizontal size rsizey set s vertical size
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 225 specifications rev. 1.1 10.2.10 blt registers set s the parameters of each register as descr ibed below : set the tcolor register with the setregister command. note that the tcolor register cannot be set at access from the cpu and by drawing commands. each register except the tcolor register is set by executing a drawing command. note that access f rom the cpu and the setregister command cannot be used. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 saddr 0240 h 0 0 0 0 0 0 0 address sstride 0244 h 0 0 0 0 int 0 srxs 0248 h 0 0 0 0 int 0 srys 024c h 0 0 0 0 int 0 daddr 0250 h 0 0 0 0 0 0 0 address dstride 0254 h 0 0 0 0 int 0 drxs 0258 h 0 0 0 0 int 0 drys 025c h 0 0 0 0 int 0 brsizex 0260 h 0 0 0 0 int 0 brsizey 0264 h 0 0 0 0 int 0 tcolor 0280 h 0 color address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets parameters for blt operations saddr sets start address of source rectangle area in byte address sstride sets stride of source srxs sets x coordinate s start position of source rectangle area srys sets y coordinate s start position of source rectangle area daddr sets start address of destination rectangle area in byte address dstride sets stride of destination drxs sets x coordinate s start position of destination rectangle area drys sets y coordinate s start position of destination rectangle area brsizex sets horizontal size of rectangle brsizey sets vertical size of rectangle tcolor sets transparent color f or indirect color, set a palette code in the lower 8 bits.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 226 specifications rev. 1.1 10.2.11 high - speed 2d line draw ing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu. register address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lx0dc 0540 h 0 0 0 0 int 0 ly0dc 0544 h 0 0 0 0 int 0 lx1dc 0548 h 0 0 0 0 int 0 ly1dc 054c h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer o r integer part of fixed point data frac fraction part of fixed point data sets coordinate s of line end points for high - speed 2dline drawing lx0dc sets x coordinate s of vertex v0 ly0dc sets y coordinate s of vertex v0 lx1dc sets x coordinate s of vertex v 1 ly1dc sets y coordinate s of vertex v1
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 227 specifications rev. 1.1 10.2.12 high - speed 2d triangle draw ing registers each register is used by the drawing commands. the registers cannot be accessed from the cpu or using the setregister command. register address 31 30 29 28 27 26 25 24 2 3 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x0dc 0580h 0 0 0 0 int 0 y0dc 0584h 0 0 0 0 int 0 x1dc 0588h 0 0 0 0 int 0 y1dc 058ch 0 0 0 0 int 0 x2dc 0590h 0 0 0 0 int 0 y2dc 0594h 0 0 0 0 int 0 address offset from drawbaseaddress s sign bit or sign extension 0 not used or 0 extension int integer or integer part of fixed point data frac fraction part of fixed point data sets coordinate s of three vertices for high - speed 2dtriangle drawing x0dc sets x coordinate s of vertex v0 y0dc se ts y coordinate s of vertex v0 x1dc sets x coordinate s of vertex v1 y1dc sets y coordinate s of vertex v1 x2dc sets x coordinate s of vertex v2 y2dc sets y coordinate s of vertex v2
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 228 specifications rev. 1.1 10.2.13 geometry control register gctr (geometry control register) register add ress geometrybaseaddress + 00 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name reserve d fo rsv fcnt nf ff fe rsv gs rsv ss rsv ps r/w rx rx rx rx rx rx rx rx r rx r rx r initial value x 0 x 011111 0 0 1 x 00 x 00 x 00 the flags and status information of the geometry section are reflected in this register. note that the flags and status information of the drawing section are reflected in ctr. bit 1 and 0 ps ( pixel engine status ) indicat e s status of pixel engine unit 00 idle 01 processing 10 reserved 11 reserved bit 5 and 4 ss ( geometry setup engine status ) indicate s status of geometry setup engine unit 00 idle 01 processing 10 processing 11 reserved bit 9 and 8 gs ( geometry engine status ) indicate s status of geometry engine unit 00 idle 01 processing 10 reserved 11 reserved bit 12 fe ( fifo empty ) indicates whether the data is contained in display list fifo (dfifod) 0 data in dfifod 1 no data in dfifod bit 13 ff ( fifo full) indicates whether display list fifo ( dfifod ) is full or not 0 dfifod not full 1 dfifod full
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 229 specifications rev. 1.1 bit 14 nf ( fifo near full) indicates free space in display list fifo ( dfifod ) 0 more than half of dfifod free 1 less than half of dfifod free bit 20 to 15 fcnt ( fifo counter) indicate s count of free stages (0 to 100000 b ) of display list fifo ( dfifod ) bit 24 fo ( fifo overflow ) indicates whether fifo overflow occurred 0 normal 1 fifo overflow
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 230 specifications rev. 1.1 10.2.14 geomet ry mode registers the setregister command is used to write values to geometry mode registers. the geometry mode registers cannot be accessed from the cpu. gmdr0 (geometry mode register for vertex) register address geometrybaseaddress + 40 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name cf df st z c f r/w rw rw rw rw rw rw initial value 0 00 0 0 0 0 this register sets the types of parameters input as vertex data and the type of pro jective transformation. bit 7 cf (color format) specifies color data format 0 independent rgb format / packed rgb format 1 reserved bit 6 and 5 df (data format) specif ies vertex coordinate s data format 00 specifies floating - point format (onl y independent rgb format can be used as color data format.) 01 specifies fixed - point format (only packed rgb format can be used as color data format.) 10 reserved 11 specifies packed integer format (only packed rgb format can be used as color data fo rmat.) cf df input data format 0 00 floating - point format + independent rgb format 01 fixed - point format + packed rgb format 10 reserved 11 packed integer format + packed rgb format 1 00 reserved 01 reserved 10 reserved 11 reserved
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 231 specifications rev. 1.1 bit 3 st (texture s and t data enable) sets whether to use texture st coordinate s 0 not use texture st coordinate s 1 uses texture st coordinate s bit 2 z (z data enable) sets whether to use z coordinate s 0 not use z coordinate s 1 uses z coordina te s bit 1 c (color data enable) sets whether to use vertex color 0 not use vertex color 1 uses vertex color bit 0 f (frustum mode) sets projective transformation mode 0 orthogonal projection transformation mode 1 perspective projection transformation mode
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 232 specifications rev. 1.1 gmdr1 (geometry mode register for line) register address geometrybaseaddress + 44 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name bo ep aa r/w w w w initial value 0 0 0 this register sets the geometry mode at line drawing. this register is sharing hardware with gmdr1e, so that if gmdr1 is changed, the same bit of gmdr1e is also changed. bit 4 bo (broken line offset) sets broken line reference position 0 broken line reference position not cleared 1 broken line reference position cleared bit 2 ep (end point mode) sets end point drawing mode note that the end point is not drawn in line strip. 0 end point not drawn 1 end point drawn bit 0 a a (anti - alias mode) sets anti - alias mode 0 anti - alias not performed 1 anti - alias performed
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 233 specifications rev. 1.1 gmdr1e (geometry mode register for line extension) register address (setgmoderegister) bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name p0 tc bc uw bm tm bp sp bo ep aa r/w w w w w w w w w w w w initial value 0 0 0 0 0 0 0 0 0 0 0 this register sets the geometry processing extended mode at line drawing. the coral extended function can be used only when the c, z, and st fields of gmdr0 are ? 0 ? . this register is sharing hardware with gmdr1, so that if gmdr1e is changed, the same bit of gmdr1 is also changed. bit31 p0 (primitive order control) sets the drawing control mode for the main, the border, and the shadow primitive. recommend to set main bit=1 in anti - aliasing and blending. 0 draws the order of, main - >border - >shadow(performance is regarded as important) 1 draws the order of , shadow - >border - >main(blending affect is regarded as important) bit30 lv (line version control) specify the coral line ? s algorithm version. v2.0 is improvement version from v1.0. recommend v2.0. 0 version 1.0 ( for backward compatibility ) 1 version 2.0 (recommended) bit 20 t c (thick line correct) sets the interpolation mode for the bold line joint 0 interpolation of bold lien joint not performed 1 interpolation of bold line joint performed (valid for only coral line) bit 16 bc (broken line correct) sets the interp olation mode for the dashed - line pattern 0 interpolation not performed 1 interpolation performed using dashed - line pattern reference address fixed mode (valid for only coral line) bit 14 uw (uniform line width) sets the line width equalization mo de 0 equalization of line width not performed 1 equalization of lien width performed (valid for only coral line) bit 13 bm (broken line mode) sets the dashed - line pattern mode 0 dashed - line pattern pasted vertical to principal axis of line (com patible with cremson) (valid for only cremson line) 1 dashed - line pattern pasted vertical to theoretical line bit 12 tm (thick line mode)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 234 specifications rev. 1.1 sets the bold line mode 0 bold line drawn vertical to principal axis of line (compatible with cremson) (crem son line) operation is not assured when tm=0 is used together with tc - 1, sp=1, or bp=1. 1 bold line drawn vertical to theoretical line. (coral line) operation is not assured when tm=1 is used together with bm=0. bit 9 bp (border primitive) sets the drawing mode for the border primitive 0 border primitive not drawn 1 border primitive drawn (valid for only coral line) bit 8 sp (shadow primitive) sets the drawing mode for the shadow primitive 0 shadow primitive not drawn 1 shadow primitive d rawn (valid for only coral line) bit 4 bo (broken line offset) sets the reference position of the dashed - line pattern 0 reference position of dashed - line pattern cleared 1 reference position of dashed - line pattern not cleared bit 2 ep (end po int mode) sets the drawing mode for the end point note that the end point is always not drawn in line strip(cremson line(tn=0)) 0 end point not drawn 1 end point drawn bit 0 aa (anti - alias mode) sets anti - alias mode 0 anti - alias not perform ed 1 anti - alias performed gmdr2 (geometry mode register for triangle) register address geometrybaseaddress + 48 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name fd cf r/w w w init ial value 0 0 this register sets the geometry processing mode when a triangle is drawn. drawing performed using commands in range from g_begin/g_begincont to g_end bit 2 fd (face definition) sets the face definition 0 face defined as state with ver texes arranged clockwise 1 face defined as state with vertexes arranged counterclockwise
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 235 specifications rev. 1.1 bit 0 cf (cull face) sets the drawing mode of the back 0 b ack drawn 1 back not drawn (value disabled for polygons)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 236 specifications rev. 1.1 gmdr2e (geometry mode register for tri angle extension) register address (setgmoderegister) bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name tl sp fd cf r/w w w w w initial value 0 0 0 0 this register sets the geome try processing extended mode at triangle drawing. in case of tl=1 with texture mapping, please set perspective correction. non - top - left - part ? s pixel quality is less than body. (using approximate calculation) bit 10 tl (top - left rule mode) sets the draw ing algorithm 0 top - left rule applied (compatible with cremson) 1 top - left rule not applied bit 8 sp (shadow primitive) sets the drawing mode for the shadow primitive 0 shadow primitive not drawn 1 shadow primitive drawn bit 2 fd (face de finition) sets the face definition 0 face defined as state with vertexes arranged clockwise 1 face defined as state with vertexes arranged counterclockwise bit 0 cf (cull face) sets the drawing mode of the back 0 b ack drawn 1 back not drawn (value disabled for polygons)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 237 specifications rev. 1.1 10.2.15 display list fifo registers dfifog (geometry displaylist fifo with geometry) register address geometry baseaddress + 400 h bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit field name dfifog r/w w initial value don?t care fifo registers for display list transfer
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 238 specifications rev. 1.1 11 timing diagram 11.1 host interface 11.1.1 cpu read/write timing diagram in sh3 mode (normally not ready mode) ( mode[2:0]=000, rdy_mode=0, bs_mode=0) t1 : read/write start cycle (xrdy in wait state) tsw*: software wait insertion cycle (1 cycle setting) thw*: hardware wait insertion cycle (xrdy cancels the wait state after the preparations) t2: read/write end cycle (xrdy ends in wait state) fig. 10.1 read /write timing diagram for sh3 (normally not ready mode) bclki a[24:2] xcs t1 tsw1 thw1 t2 t1 tsw1 thw1 thw2 th w3 t2 xbs xrd hi - z hi - z d[31:0] valid data valid data hi - z xwe[3:0] xwait d[31:0] softwait hardwait notwait hi - z softwait hardwait hardwait hardwait valid data in valid data in hi - z ? : xwait sampling in sh3 mode : soft wait (1 cycle) in sh3 mode not wait at read at write
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 239 specifications rev. 1.1 11.1.2 cpu read/write timing diagram in sh3 mode (normally ready mode) ( mode[2:0]=000, rdy_mode=1, bs_mode=0) t1: read/write start cycle (xrdy in not wait state) tsw*: software wait inser tion cycle (2 - cycle setting required) thw*: h ardware wait insertion cycle (in hardware state when the immediate accessing is disabled) t2: read/write end cycle (xrdy ends in not wait state) fig. 10 .2 read/write timing diagram for sh3 (normally ready mode ) hi - z hi - z hi - z bclki a[24:2] xcs x bs xrd xwe[3:0] d[31:0] xwait d[31:0] ? : xwait sampling in sh3 mode : soft wait (2 cycles) in sh3 mode softwait softwait notwait t1 tsw1 tsw2 t2 t1 tsw1 tsw2 thw1 thw2 t2 softwait softwait hardwait hardwait notwait valid data in valid data valid data valid data in hi - z hi - z at write at read
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 240 specifications rev. 1.1 11.1.3 cpu read/write timing diagram in sh4 mode (normally not ready mode) ( mode[2:0]=001, rdy_mode=0, bs_mode=0) t1: read/write start cycle (xrdy in the not ready state) tsw*: software wait insertion cycle (1 cycle) twh*: hardware wait inser tion cycle (xrdy asserts ready after the preparations) t2: read/write end cycle (xrdy ends in not ready state) fig. 10 .3 read/write timing diagram for sh4 mode (normally not ready mode) hi - z valid data in valid data out hi - z bclki a[24:2] xcs xbs xrd xwe[3:0] d[31:0] xrdy d[31:0] ? : xrdy sampling in sh4 mode : soft wait (1 cycle) in sh4 mode softwaiit hardwait ready t1 tsw1 thw1 t2 t1 tsw1 thw1 thw2 thw3 t2 valid data out hi - z softwait hardwait hardwait hardwait ready valid data in at read at write
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 241 specifications rev. 1.1 11.1.4 cpu read/write timing diagram in sh4 mode (normally ready mode) ( mode[2:0]=001, rdy_mode=1, bs_mode=0) t1: read/write start cycle (xrdy in ready state) tsw*: software wait insertion cycle (2 - cycle setting required) twh*: h ardware wait insertion cycle (xrdy asserts ready after the preparations) t2 : read/write end cycle (xrdy ends in ready state.) fig. 10 .4 cpu read/write timing diagram for sh4 mode (normally ready mode) hi - z bclki a[24:2] xcs xbs xrd xwe[3:0] d[31:0] xrdy d[31:0] ? : xrdy sampling in sh4 mode : soft wait (2 cycles) in sh4 mode softwaiit softwait ready t1 tsw1 tsw2 t2 t1 tsw1 tsw2 thw1 thw2 t 2 softwait softwait hardwait hardwait ready valid data out valid data out valid data in valid data in hi - z hi - z at read at write
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 242 specifications rev. 1.1 11.1.5 cpu read/write timing diagram in v832 mode (normally not ready mode) ( mode[2:0]=010, rdy_mode=0, bs_mode=0) t 1: read/write start cycle (xready in not ready state) tsw*: software wait insertion cycle twh*: h ardware wait insertion cycle (xready asserts ready after the preparations) t2: read/write end cycle (xready end s in not ready state) notes: 1.the xxxben signa l is used only for a write from the cpu; it is not used for a read from the cpu. 2.the cpu always inserts one cycle wait after read access. fig. 10 .5 read/write timing diagram in v832 mode (normally not ready mode) bclki a[23:2] xcs xb1cyst xready d[31:0] ? : xready sampling in v832 mode : soft wait (1 cycle) in v832 mode softwaiit hardwait ready t1 tsw1 thw1 t2 t1 tsw1 thw1 thw2 thw3 t2 softwait hardwait hardwait hardwait ready valid data out valid data out valid data in hi - z hi - z valid data in hi - z hi - z at read at write d[31:0] xmrd(xiord) xmwr(xiowr) xxxben[3:0]
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 243 specifications rev. 1.1 11.1.6 cpu read/write timing diagram in v832 mode (normally ready mode) ( mode[2:0]=010, rdy_mode=1, bs_mode=0) t1: read/write start cycle (xready in ready state) tsw*: software wait insertion cycle (2 - cycle setting required) twh*: h ardware wait insertion cycle (xready asserts ready a fter the preparations) t2: read/write end cycle (xready end s in ready state) notes: 1.the xxxben signal is used only for a write from the cpu; it is not used for a read from the cpu. 2.the cpu always inserts one cycle wait after read access. fig. 10 .6 r ead/write timing diagram in v832 mode (normally ready mode) bclki a[23:2] xc s xbcyst d[31:0] xready d[31:0] ? : x ready sampling in v832 mode : soft wait (2 cycles) in v832 mode softwaiit softwait re ady t1 tsw1 tsw2 t2 t1 tsw1 tsw2 thw1 thw2 t2 softwait softwait hardwait hardwait ready valid data out valid data out valid data in hi - z hi - z valid data in hi - z hi - z at read at write xmrd(xiord) xmwr(xiowr) xxxben[3:0])
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 244 specifications rev. 1.1 11.1.7 cpu read/write timing diagram in sparclite (normally not ready mode) ( mode[2:0]=011, rdy_mode=0, bs_mode=0) t1: read/write start cycle (ready# in not ready state) tsw*: software wait insertion cycle twh*: h ardware wait insertion cycle (ready# asserts ready after the preparations ) t2: read/write end cycle (ready# end s in not ready state) note: be# signal is used only for a write from the cpu; it is not used for a read from the cpu. fig. 10 .7 read/write timing diagram in sparclite (normally not ready mode) hi - z clkini adr[2 3:2] cs# as# d[31:0] ready # d[31:0] ? : ready# sampling in sparclite : soft wait (1 cycle) in sparclite softwaiit hardwait ready t 1 tsw1 thw1 t2 t1 tsw1 thw1 thw2 thw3 t2 softwait hardwait hardwait hardwait ready valid data valid data valid data in hi - z hi - z valid data in hi - z hi - z rdwr# rdwr# be[3:0]# at read at write
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 245 specifications rev. 1.1 11.1.8 cpu read/write timing diagram in sparclite (normally ready mode) ( mode[2:0]=011, rdy_mode=1, bs_mode=0) t1: read/write start cycle (ready# in ready state) tsw *: software wait insertion cycle (2 - cycle setting required) twh*: h ardware wait insertion cycle (ready# asserts ready after the preparations) t2: read/write end cycle (ready# end s in ready state) note: be# signal is used only for a write from the cpu; it i s not used for a read from the cpu. fig. 10 .8 read/write timing diagram in sparclite (normally ready mode) hi - z clkini adr[23: 2] cs# as# d[31:0] ready# d[31:0] ? : ready# sampling in sparclite : soft wait (1 cycle) in sparclite softwaiit softwait ready t1 tsw1 tsw1 t2 t1 tsw1 tsw1 thw1 thw2 t2 softwait hardwait hardwait hardwait ready valid data valid data valid data in hi - z hi - z valid data in hi - z hi - z at read at write rdwr# rdwr# be#[3:0]
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 246 specifications rev. 1.1 11.1.9 sh4 single - address dma write (transfer of 1 long word) ? : dreq sampling and channel priority determination for sh mode (dreq = level d etection) *1: in the cycle steal mode, even when dreq is already asserted at the 2nd dreq sampling, the right to use the bus is returned to the cpu temporarily . in the burst mode, dmac secures the right to use the bus unless dreq is negated. fig. 10 .9 s h4 single - address dma write (transfer of 1 long word) coral writes data according to the dtack assert timing. when data cannot be received, the dreq signal is automatically negated. and then the dreq signal is reasserted as soon as data reception is rea dy . dmac cpu *1 dmac cpu *1 bclkin d[31:0] dreq drack dtack a cceptance acceptance acceptance bus cycle
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 247 specifications rev. 1.1 11.1.10 sh4 single - address dma write (transfer of 8 long words) ? : dreq sampling and channel priority determination for sh mode (dreq = level detection) fig. 10 .10 sh4 single - address dma write (transfer of 8 long words) after the cpu has asserte d drack, coral negates dreq and receives 32 - byte data in line with the dtack assertion timing. as soon as the next data is ready to be received, coral reasserts dreq but the reassertion timing depends on the internal status. dmac cpu cpu bclkin d[31 :0] dreq drack dtack acceptance bus cycle acceptance
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 248 specifications rev. 1.1 11.1.11 sh3/4 dual - address dma (trans fer of 1 long word) for the coral , the read/write operation is performed according to the sram protocol. fig. 10 .11 sh3/4 dual - address dma (transfer of 1 long word) in the dual - address mode, the dreq signal is kept asserted until the transfe r ends by default. consequently, when coral cannot return the r eady signal immediately, in order to negate the dreq signal set the dbm register. 11.1.12 sh3/4 dual - address dma (transfer of 8 long words) for the coral , the read/write operation is perf ormed according to the sram protocol. fig. 10 .12 sh3/4 dual - address dma (transfer of 8 long words) in the dual - address mode, the dreq signal is kept asserted until the transfer ends by default. consequently, when coral cannot return the r eady signal im mediately, in order to negate the dreq signal set the dbm register. bclkin d[31:0] a[24:2] read dest ination address write source address dreq destination address source address read write bclkin d[31:0] a[24:2] read 1 source address ??? ??? ??? ??? destination address ??? ??? dreq read 2 read 8 write 1 write 2 write 8
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 249 specifications rev. 1.1 11.1.13 v832 dma transfer for the coral , the read/write operation is performed according to the sram protocol. fig. 10 .13 v832 dma transfer in the dual - address mode, the dreq signal is kept asserted until the transfer ends by default. consequently, when coral cannot return the r eady signal immediately, in order to negate the dreq signal set the dbm register. bclkin d[31:0] a[23:2] dmarq dmaak read destination address write source address destination address source address read write
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 250 specifications rev. 1.1 11.1.14 sh4 single - address dma transfer end timing ? : dreq sampling and channel priority determination for sh mode (dreq = level detection) fig. 10 .14 sh4 single - address dma transfer end timing dreq is negated three cycles after drack is written as the last data. 11.1.15 sh3/4 dual - address dma transfer end timing for the coral , the read/write operation is performed according to the sram protocol. fig. 10 .15 sh3/4 dual - address dma transfer end timing dreq is negated three cycles after drack is written as the last data. note: when the dual address mode (dma) is used , the dtack signal is not used. bclkin d[31:0] dreq drack dtack acceptance last data acceptance bclkin d[31:0] a[24:2] read destination address source address dreq drack dtack write
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 251 specifications rev. 1.1 11.1.16 v832 dma transfer end timing for the coral , the read/write operation is performed according to the sram protocol. fig. 10 .16 v832 dma transfer end timing dmmak and xtc are logic anded inside coral to end d ma. bclkin d[31:0] a[24:2] dmarq dmaak xtc read destination address write source address
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 252 specifications rev. 1.1 11.1.17 sh4 dual dma write without ack clk /dreq /bs /rd /we[3:0] address /cs(coral) right to use bus sar dar dmac cpu 1 2 3 4 when coral can not receive data immediately, dreq neg ation continues. while dreq is issued at each write access to coral, dreq is negated at every four cycles.. fig. 10.17 dreq negate t iming for each transfer at each dma transfer, dreq is negated and then reasserted at the next cycle. only the fifo address can be used as the destina tion address. when coral cannot receive data immediately, dreq negation continues. at that time, the negate timing is not only above diagram.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 253 specifications rev. 1.1 11.1.18 dual - address dma (without ack) end timing /dreq right to use bus cpu cpu cpu dmac dmac fig. 10.18 dual - a ddress dma (without ack) e nd timing example: dma operation when dma transfer performed twice ( 1) the cpu accesses the dreq issue register (drq) of coral to issue dreq. ( 2) the right to use bus is transferred from the cpu to the dmac. ( 3) in the first dmac cycle, write is performed to c oral and dreq is negated; dreq is reasserted in the next cycle. ( 4) the right to use bus is returned to the cpu and the dreq edge is detected, so the right to use bus is transferred to the dmac. ( 5) the second write operation is performed and dreq is negated, but dreq is reasserted because c oral does not recognize that the transfer has ended. ( 6) the right to use bus is transferred to the cpu, so the cpu writes to the dts register of coral to negate dreq.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 254 specifications rev. 1.1 11.2 graphics memory interface the coral access timing and graphics memory access timing are explained here. 11.2.1 timing of read access to same row address fig. 10.19 timing of read access to same r ow a ddress the above timing diagram shows that read access is made four times fro m coral to the same row address of sdram. the actv command is issued and then the read command is issued after trcd elapses. then data that is output after the elapse of cl after the read command is issued is captured into coral. mclko cl trcd ma mwe mcas mras md row col data data data data col col col row: row address col: column address data: read data trc d: ras to cas delay time cl: cas latency dqm *timing when cl2 operating
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 255 specifications rev. 1.1 11.2.2 timing of read access to different row addresses fig. 10.20 timing of r ead a ccess to d ifferent r ow a ddresses the above timing diagram shows that read access is made from coral to different row addresses of sdram. the first and next address to be read fall ac ross a n sdram page boundary, so the pre - charge command is issued at the timing satisfying tras, and then after the elapse of trp, the actv command is reissued, and then the read command is issued. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time cl: cas latency trp: ras precharge time mclko tras cl trcd ma mwe mc as mras md row col data trp row col trcd cl data dqm *timing when cl2 operating
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 256 specifications rev. 1.1 11.2.3 timing of write access to same row address fig. 10.21 timing of write access to same r ow a ddress the above timing diagram shows that write access is made form times form coral to the same row address of sdram. the actv command is issued, and then after the elapse of trcd, the write com mand is issued to write to sdram. mclko trcd ma mwe mcas mras md row col data data data data col col col row: row address col: column address data: read data trcd: ras to cas delay time dqm
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 257 specifications rev. 1.1 11.2.4 timing of write access to different row addresses fig. 10.22 timing of write a ccess to d ifferent r ow a ddresses the above timing diagram shows that write access is made from coral to different row ad dresses of sdram. the first and next address to be write fall across a n sdram page boundary, so the pre - charge command is issued at the timing satisfying tras, and then after the elapse of trp, the actv command is reissued, and then the write command is i ssued. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time trp: ras precharge time mclko tras trcd ma mwe mcas mras md row col data trp row col trcd data dqm
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 258 specifications rev. 1.1 11.2.5 timing of read/write access to same row address fig. 10.23 timing of r ead/ w rite a ccess to s ame r ow a ddress the above timing diagram shows that write access is made immediately after read access is made from coral to the same r ow address of sdram. read data is output from sdram, lowd elapses, and then the write command is issued. row: row address col: column address data: read data tras: ras active time trcd: ras to cas delay time cl: cas latency trp: ras precharge time lowd: last output to write command delay mclko cl trcd ma mwe mcas mras md row col data dat a dqm timing when cl2 operating lowd col
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 259 specifications rev. 1.1 11.2.6 delay between actv commands fig.10.24 delay between actv commands the actv command is issued from coral to the row address of sdram after the elapse of trrd after issuance of the previous actv command. 11.2.7 delay between refresh command and next actv command fig. 10.25 delay between refresh command and next actv command the actv command is issued after the elapse of trc af ter issuance of the refresh command. row: row address trrd: ras to ras bank active delay time mclko ma mwe mcas mras row row trrd row: row address trc: ras cycle time mclko ma mwe mcas mras row trc
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 260 specifications rev. 1.1 11.3 display timing 11.3.1 non - interlace mode fig. 10 . 26 non - interlace timing in the above diagram, vtr, hdp, etc., are the setting values of their associated registers. the vsync/frame interrupt is asserted when display of the last raster ends. when updating display parameters, synchronize with the frame interrupt so no display disturbance occurs. calculation for the next frame is started immediately after the vertical synchronization pulse is asserted, so the parameters must be updated by the time that calculation is started. ri/gi/bi dispe hsync vsync ri/gi/bi dispe hsync dclko ri/gi/bi dispe vtr+1 rasters vsp+1 rasters vdp+1 rasters vsw+1 rasters assert frame interrupt assert vsync interrupt latency=14clocks hdp+1 clocks hsp+1 clocks htp+1 clocks hsw+1 clocks 1 2 3 n - 2 n - 1 n = hdp+1
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 261 specifications rev. 1.1 11.3.2 interlace video mode fig. 10 . 27 interlace video timing in the above diagram, vtr, hdp, etc., are the setting values of their associated registers. the interlace mode also operates at the same timing as the interlace video mode. the only difference between the two modes is the output image data. vdp+1 rasters vsync hsync vsp+1 rasters vtr+1 rasters (odd field) vsw+1 rasters vtr+1 rasters (even field) vsw+1 rasters vsync hsync vdp+1 rasters vsp+1 rasters assert vsync interrupt asser t vsync interrupt assert frame interrupt ri/gi/bi ri/gi/bi
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 262 specifications rev. 1.1 11.3.3 composite synchronous signal when the eeq bit of the dcm register is ? 0 ? , the csync signal output waveform is as shown below. fig 10.28 composite synchronous signal without equalizing pulse when the eeq bit of the dcm register is ? 1 ? , the equalizing pulse is inserted into the csync signal, producing the waveform shown below. fig 10.29 composite synchronous signal with equalizing pulse the equalizing pulse is inserted when the vertical blanking time period starts. it is also inserted three times after the vertical synchronization time period has elapsed. cautions 11.4 cpu cautions csync vsync csync vsync odd field even field odd field even field csync vsync csync vsync odd field even field odd field even field
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 263 specifications rev. 1.1 1) enable the ha rdware wait for the areas to which coral is connected . when the normal ly not ready mode ( rdy_mode = 0) is used, set the software wait count to ?1?. when the normal ly ready mode ( rdy_mode = 1) is used, set the count to ?2?. when the normally ready mode i s used (rdy_mode = 1) and bs_mode = l, set the software wait to 2. when the normally ready mode is enabled and bs_mode = h , set the software wait to ? 3 ? . 2) when starting dma by issuing an external request, do so after setting the transfer count register (dtcr) and mode setting register (dsur) of coral to the same value as the cpu setting. in the dual dma without ack mode or v832 mode, there is no need to set dtcr. 3) when coral is read - /write - accessed from the cpu during dma transfer, do not access the r egisters and memories related to dma transfer. if these registers and memories are accessed, reading and writing of the correct value is not assured. 4 ) set dreq (dmarq) to ? low ? level detection. 5 ) set the dack/drack of sh to high active output, dmaak of v832 to high active, and x tc of v832 to low active. 11.5 sh3 mode 1) when the xrdy pin is low, it is in the wait state. 2) dma transfer in the single - address mode is not supported. 3) dma transfer in the dual - address mode supports the direct address transfe r mode, but does not support the indirect address transfer mode. 4) 16 - byte dma transfer in the dual - address mode is not supported. 5) the xint signal asserts low active signal . 11.6 sh4 mode 1) when the xrdy pin is low, it is in the ready state. 2) at dma t ransfer in the single - address mode, transfer from the main memory (sh memory) to fifo of coral can be performed, but transfer from coral to the main memory cannot be performed. 3) dma transfer in the single - address mode is performed in units of 32 bits or 32 bytes. 4) sh4 - mode 32 - byte dma transfer in the dual - address mode supports inter - memory transfer, but does not support transfer from memory to fifo. 5) the xint signal asserts low active signal .
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 264 specifications rev. 1.1 11.7 v832 mode 1) when the xrdy pin is low, it is in the ready state. 2) set the active level of dmaak to high active in v832 mode. 3) dma transfer supports the single transfer and demand transfer mode s . 4) the xint signal asserts high active signal . set the v832 - mode registers to high level trigger. 11.8 sparclite 1) when the xrdy pin is low, it is in the ready state. 2) the sparclite does not support the dma transfer that issues the dreq. 3) the xint signal asserts low active signal . 11.9 supported dma transfer modes single address mode dual address mode sh3 not supp ort ed direct address transfer mode support ed ; indirect address transfer mode not support ed . transfer is performed in 32 - bit units. cycle steal mode and burst mode support ed . sh4 transfer performed in units of 32 bits or 32 bytes cycle steal mode and burst mode support ed transfer is performed in 32 - bit units. transfer to memory is performed in 32 - byte units. transfer to fifo not support ed . cycle steal mode and burst mode support ed . v832 transfer is performed in 32 - bit units. single transfer mode and demand transfer mode support ed . sparc lite
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 265 specifications rev. 1.1 12 electrical characteristics 12.1 introduction the values in this chapter are the final specification for coral - lq. 12.2 maximum rating maximum rating parameter symbol maximum rating unit power supply voltage v ddl * 1 v ddh - 0.5 < v ddl < 2.5 - 0.5 < v ddh < 4.0 v input voltage v i - 0.5 < v i < v ddh +0.5 (<4.0) v output current i o 13 ma ambient for storage temperature tst - 55 < tst < +125 c *1 includes pll power supply
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 266 specifications rev. 1.1 12.3 recommended operating conditions 12.3.1 recommended oper ating conditions recommended operating conditions rating parameter symbol min. typ. max. unit supply voltage v ddl *1 v ddh 1.65 3.0 1.8 3.3 1.95 3.6 v input voltage (high level) v ih 2.0 v ddh + 0.3 v input voltage (low level) v il - 0.3 0.8 v ambient temperature for operation ta - 40 85 c *1 includes pll power supply 12.3.2 note at power - on there is no restriction on the sequence of power - on/power - off between v ddl and v ddh . however, do not apply only v ddh for more than a few seconds. do not input hsync, v sync, and eo signals when the power supply voltage is not applied. (see the input voltage item in maximum rating .) th ere are th ree reset sequences as described next page. and please input at least 10 bclk cycles to bclk pin before xrst negated.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 267 specifications rev. 1.1 (1) trst , s, xrst are changed from ? low ? to ? high ? levels in this order: immediately after power - on, input the ? low ? level to the trst pin for 500 ns or more. after the trst pin is set to ? high ? level, input the ? low ? level to the s pin for 500 ns or more . after the s pin is set to ? high ? level, input the ? low ? level to the xrst pin for 300 m s or more . (2) s is changed from ? low ? to ? high ? levels and then trst and xrst are changed from ? low ? to ? high ? levels simultaneously (trst = xrst is possible): immediately after powe r - on, input the ? low ? level to the s pin for 500 ns or more . after the s pin is set to ? high ? level, input the ? low ? level to the trst and xrst pins for 300 m s or more . there is no restriction on the input sequence to the xrst and trst pins. (3) s and trst are changed from ? low ? to ? high ? levels simultaneously and then xrst is changed from ? low ? to ? high ? levels (s = trst is possible): immediately after power - on, input the ? low ? level to the s and trst pins for 500 ns or mo re. after the s and trst pins are set to ? high ? level, input the ? low ? level to the xrst pin for 300 m s or more . there is no restriction on the input sequence to the s and trst pins. trst s xrst more than 500ns 300 m s more than 500ns s trst xrst more than 500ns 300 m s s trst xrst more than 500ns 300 m s
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 268 specifications rev. 1.1 12.4 dc characteristics 12.4.1 dc characteristics measuring c ondition : v ddl = 1.8 1.5 v, v ddh = 3.3 0.3 v, v ss = 0.0 v, ta = - 40 to +85 c rating parameter symbol condition min. typ. max. unit output voltage *1 (?high? level) v oh i oh = - 100ua v ddh - 0.2 v ddh v output voltage *2 (?low? level) v ol i ol =100ua 0.0 0.2 v output curren t (?high? level) -- v ddh =3.3v 0.3v (*1) ma output current (?low? level) -- v ddh =3.3v 0.3v (*1) ma input leakage current il 5 a pin capacitance c 16 pf *1: please refer ? v - i characteristics diagram ? . l type : output characteristics of md0 - 63, md qm0 - 7, r2 - 7, g2 - 7, b2 - 7 pins m type : output characteristics of pins other than signals indicated by l type and h type h type : output characteristics of xint, dreq, xrdy, mclko pins
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 269 specifications rev. 1.1 12.4.2 v - i characteristics diagram condition max: process=slow, ta=85 c , v dd =3.6 v typ: process=typical, ta=25 c , v dd =3.3v min: process=fast, ta= - 40 c , v dd =3.0v fig. v - i characteristics l, m type condition max: process=slow, ta=85 c , v dd =3.6v typ: process=typical, ta=25 c , v dd =3.3v min: process=fast, ta= - 40 c , v dd =3.0v fig. v - i cha racteristics h type
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 270 specifications rev. 1.1 12.5 ac characteristics 12.5.1 host interface clock rating parameter symbol condition min. typ. max. unit bclki f requency f bclki 100 mhz bclki h - width t hbclki 1 ns bclki l - width t lbclki 1 ns host interface signals ( operatin g condition: external load = 20 pf ) rating parameter symbol condition min. typ. max. unit address set up time t ads 3.0 ns address hold time t adh 0. 0 ns xbs set up time t bss 3 .0 ns xbs hold time t bsh 0 .0 ns xcs set up time t css 3 .0 ns xcs hold time t csh 0 .0 ns xrd set up time t rds 3 .0 ns xrd hold time t rdh 0 .0 ns xwe set up time t wes 5 .0 ns xwe hold time t weh 0.0 ns write data set up time t wds 3.5 ns write data hold time t wdh 0 .0 ns dtack set up time t d aks 3 .0 ns dtack hold time t dakh 0 .0 ns drack set up time t drks 3 .0 ns drack hold time t drkh 0 .0 ns read data delay time (for xrd) t rddz 4.5 1 0 . 5 ns read data delay time t rdd * 2 4.5 9 .5 ns xrdy delay time (for xcs) t rdydz 3.5 7 .0 ns xrdy delay time t rdyd 2.5 6.0 ns xint delay time t intd 3.0 7.0 ns dreq delay time t dqrd 3 .5 7.0 ns mode hold time t modh *1 20.0 ns *1 hold time require d for canceling reset * 2 valid data is output at assertion of xrdy and is retained until xr d is negated.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 271 specifications rev. 1.1 12.5.2 video interface clock rating parameter symbol condition min. typ. max. unit clk frequency f clk 14.3 18 mhz clk h - width t hclk 25 ns clk l - width t lclk 25 ns dclki frequency f dclki 67 mhz dclki h - width t hdclki 5 ns dcl ki l - width t ldclki 5 ns dclko frequency f dclko 67 mhz input signals rating parameter symbol condition min. typ. max. unit t whsync0 *1 3 clock hsync input pulse width t whsync1 *2 3 clock hsync input setup time t shsync *2 10 ns hsync input hold time t hhsync *2 10 ns vsync input pulse width t whsync1 1 hsync 1 cycle *1 applied only i n pll synchronization mode (cks = 0), reference clock output from internal pll ( cycle = 1/14*fclk) *2 applied only i n dclki synchronization mode (ck s = 1), reference clock = dclki output signals rating parameter symbol condition min. typ. max. unit rgb output delay time t rgb 2 1 0 ns dispe output delay time t deo 2 10 ns hsync output delay time t dhsync 2 10 ns vsync output delay time t dv sync 2 10 ns csync output delay time t dcsync 2 10 ns gv output delay time t dgv 2 10 ns
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 272 specifications rev. 1.1 12.5.3 graphics memory interface condition: clock frequency=133mhz, 100mhz, bclk. printed - wiring is isometry. an assumed external capacitance an assumed e xternal capacitance parameter min typ max unit board pattern 5.0 15.0 pf sdram (clk) 2.5 4.0 pf sdram (d) 4.0 6.5 pf sdram (a, dqm) 2.5 5.0 pf clock rating parameter symbol condition min. typ. max. unit mclk o frequency f m clko *1 mhz m clk o h - w idth t hmclko 1 .0 ns m clk o l - width t lmclko 1 .0 ns mclki frequency f m clki *1 mhz mclki h - width t hmclki 1.0 ns mclki l - width t lmclki 1.0 ns *1 for the bus - asynchronous mode, the frequency is 1/3 of the oscillation frequency of the internal pll. for the bus - synchronous mode, the frequency is the same as the frequency of bclki. input signals rating parameter symbol condition min. typ. max. unit md input data setup time t mdids *2 2.0 ns md input data hold time t mdidh *2 0.7 ns * 2 it means against mclki.
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 273 specifications rev. 1.1 there are some cases regarding ac specifications of output signals. the following tables shows typical six cases of external sdrfam capacitance. (1) external sdram capacitance case 1 external sdram capacitance sdram x1 total ca pacitance unit mclko 9.9pf (dram clk 2.5pf, board pattern 5pf) pf ma,mras,mcas,mwe 7.5pf (dram a.dqm 2.5pf, board pattern 5pf) pf md,dqm 9.0pf (dram d 4pf, board pattern 5pf) pf output signals rating *1 parameter symbol condition min. typ. ma x. unit mclki signal delay time against mclko t d id 0 4.2 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.0 ns mdqm a ccess time t mdqmd 1.1 5.4 ns md o utput access time t mdod 1.1 5.4 ns (2) external sdram capacitance case 2 external sdram capacitance sdram x1 total capacitance unit mclko 25.4pf (dram clk 4.0pf, board pattern 15pf) pf ma,mras,mcas,mwe 20.0pf (dram a.dqm 5pf, board pattern 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.5 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.2 ns mdqm a ccess time t mdqmd 1.2 5.5 ns md o utput access time t mdod 1.2 5.5 ns
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 274 specifications rev. 1.1 (3) external sdram capacitance case 3 e xternal sdram capacitance sdram x2 total capacitance unit mclko 12.4pf (dram clk 2.5pf x2, board pattern 5pf) pf ma,mras,mcas,mwe 10.0pf (dram a.dqm 2.5pf x2, board pattern 5pf) pf md,dqm 9.0pf (dram d 4pf, board pattern 5pf) pf output signals rating *1 paramet er symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 4.1 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.0 ns mdqm a ccess time t mdqmd 1.1 5.2 ns md o utput access time t mdod 1.1 5.2 ns (4) external sdram capacitance case 4 external sdram capacitance sdram x2 total capacitance unit mclko 29.4pf (dram clk 4.0pf x2, board pattern 15pf) pf ma,mras,mcas,mwe 25.0pf (dram a.dqm 5pf x2, board pattern 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15p f) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.4 ns ma, mras, mcas, mwe a ccess time t m ad 1.1 5.4 ns mdqm a ccess time t mdqmd 1.1 5.5 ns md o utput access time t mdo d 1.1 5.5 ns
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 275 specifications rev. 1.1 (5) external sdram capacitance case 5 external sdram capacitance sdram x4 total capacitance unit mclko 17.4pf (dram clk 2.5pf x4, board pattern 5pf) pf ma,mras,mcas,mwe 15.0pf (dram a.dqm 2.5pf x4, board pattern 5pf) pf md,dqm 9.0pf ( dram d 4pf, board pattern 5pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.9 ns ma, mras, mcas, mwe a ccess time t m ad 1.0 5.2 ns mdqm a ccess time t mdqmd 1.0 5.0 ns md o utput access time t mdod 1.0 5.0 ns (6) external sdram capacitance case 6 external sdram capacitance sdram x4 total capacitance unit mclko 37.3pf (dram clk 4.0pf x4, board pattern 15pf) pf ma,mras,mcas,mwe 35.0pf (dram a.dqm 5pf x4, board patter n 15pf) pf md,dqm 21.5pf (dram d 6.5pf, board pattern 15pf) pf output signals rating *1 parameter symbol condition min. typ. max. unit mclki signal delay time against mclko t d id 0 3.4 ns ma, mras, mcas, mwe a ccess time t m ad 1.2 5.7 ns mdqm a ccess time t mdqmd 1.0 5.3 ns md o utput access time t mdod 1.0 5.3 ns
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 276 specifications rev. 1.1 12.5.4 pll specifications parameter rating description input frequency (typ.) 14.31818 mhz output frequency 400.9090 mhz 28 duty ratio 101. 6 to 93. 0 % h/l pulse width ratio of pll output jitter 60 to - 60 ps frequency tolerant of two consecutive clock cycles clksel1 clksel1 input frequency assured operation range (*1) l l 13.5 mhz 13.365 to 13.5 mhz l h 14.32 mhz 14.177 to 14.32 mhz h l 17.73 hz 17.553 to 17.73 mhz *1 assure d operation input frequency range: standard value ? 1%
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 277 specifications rev. 1.1 12.6 ac characteristics measuring conditions 80 % 20 % 80 % 20 % (v ih +v il )/ 2 v dd / 2 v dd / 2 t r t f tphl tplh v dd / 2 tpzl tplz v dd / 2 0.5 v 0.5 v tphz tpzh input output output enabled output disabled tr, tf 5 ns v ih =2.0 v, v il = 0.8v ( 3.3 - v cmos interface input )
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 278 specifications rev. 1.1 12.7 timing diagram 12.7.1 host interface clock mode hold time xint output delay times bclki 1/f bclki t lbclki t hbclki xreset t modh mode bclk xint t int
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 279 specifications rev. 1.1 host bus ac timing (norma lly not ready) t rdydz t rddz bclki d(ou tput) t rddz xrd (rdxwr) hi - z xrdy t rdyd t rdyd t rdd output data hi - z a xbs xcs xwe (xmwe) hi - z d(input) t rdydz t adh t ads t bsh t bss t bsh t bss t csh t css t wes t weh t wds t wdh t rds t rdh t rdydz xwait t rdyd t rdyd hi - z hi - z hi - z t1 tsw1 thw1 t2 t rdydz
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 280 specifications rev. 1.1 host bus ac timing (normally ready) bclki a t adh t ads t bsh t bss t bsh t bss t1 tsw1 tsw2 t2 thw1 t rddz d(output) t rddz xrd (rdxwr) t rdd output data hi - z xbs xcs xwe (xmwe) d(input) t csh t css t wes t weh t wds t wdh t rds t rdh xrdy t rdyd t rdyd xwait t rdyd t rdyd hi - z t rdydz hi - z t rdydz hi - z hi - z t rdydz t rdydz hi - z
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 281 specifications rev. 1.1 dma ac timing *: the above timing diagram for the d pin is that of when a single dma is used. when a dual dma is used, see the host bus - timing diagram. bclki d(input) dtack (xtc) t wdh t wds t dakh t daks t dakh t daks t rrkh t drks t wdh dreq drack (dmaak ) t drqd t rrkh t drks t drqd
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 282 specifications rev. 1.1 12.7.2 video interface clock hsync signal setup/hold output signal delay dclko t rgb , t deo , t dhsync, t dvsync , t dcsync, t dgv dr7 - 2, dg7 - 2 db7 - 2 md63 - 58* hsync (output) vsync (output) csync, de gv *valid if xrgben = 0 clk 1/f clk t lclk t hclk v ih v il dclki t hdclki t ldclki 1 / f dclki t shsyn t hhsyn hsync (input)
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 283 specifications rev. 1.1 12.7.3 graphics memory interface clock input signal setup/hold time mclki signal delay mclko, mclki 1/f mclko, 1/f mclki t hmclko, t hmclki t lmclko, t lmclki mclki t mdids md t mdidh input data mclko t oid mclki
fujitsu limited preliminary and confidential MB86293 coral_lq graphics controller 284 specifications rev. 1.1 output signal de lay mclko t mad, t mdod, t mdqmd ma, mras, mcas, mwe, md, mdqm
the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of the information or package dimensions in this document. fujitsu semiconductor data sheet quad flat package 256 pin plastic 256-pin plastic qfp lead pitch 0.40 mm package width package length 28.0 28.0 mm lead shape gullwing sealing method plastic mold mounting height 4.03 mm max weight 5.74g remark low heat resistance type code(reference) p-fqfp256-28 28-0.40 256-pin plastic qfp (fpt-256p-m09) (fpt-256p-m09) c 2000 fujitsu limited f256025s-c-2-3 details of "a" part (stand off) (.147 .012) 3.73 0.30 0.40 +0.10 C 0.15 +.004 C .006 .016 0.18 0.05 (.007 .002) m 0.07(.003) 0.40(.016) 256 193 192 129 128 65 64 lead no. 1 index 0.145 0.055 (.006 .002) 0.08(.003) "a" 0 ?~ 8 ? (0.50(.020)) 0.60 0.15 (.024 .006) 0.25(.010) 28.00 0.10(1.102 .004)sq 30.60 0.20(1.205 .008)sq (mounting height) dimensions in mm (inches). fpt-256p-m09 0010 * pins width and pins thickness include plating thickness.

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